#ifndef REGISTERADDRESS_H #define REGISTERADDRESS_H enum class Register : uint32_t { EventReadOutBuffer = 0x0000, /// R ///========== Channel or Group ChannelDummy32 = 0x1024, /// R/W InputDynamicRange = 0x1028, /// R/W ChannelPulseWidth = 0x1070, /// R/W ChannelTriggerThreshold = 0x1080, /// R/W CoupleSelfTriggerLogic = 0x1084, /// R/W ChannelStatus = 0x1088, /// R AMCFirmwareRevision = 0x108C, /// R ChannelDCOffset = 0x1098, /// R/W ChannelADCTemperature = 0x10A8, /// R ChannelSelfTriggerRateMeter = 0x10EC, /// R ///========== Board BoardConfiguration = 0x8000, /// R/W BufferOrganization = 0x800C, /// R/W CustomSize = 0x8020, /// R/W ADCCalibration = 0x809C, /// W AcquisitionControl = 0x8100, /// R/W AcquisitionStatus = 0x8104, /// R SoftwareTrigger = 0x8108, /// W GlobalTriggerMask = 0x810C, /// R/W FrontPanelTRGOUTEnableMask = 0x8110, /// R/W PostTrigger = 0x8114, /// R/W LVDSIOData = 0x8118, /// R/W FrontPanelIOControl = 0x811C, /// R/W ChannelEnableMask = 0x8120, /// R/W ROCFPGAFirmwareRevision = 0x8124, /// R EventStored = 0x812C, /// R VoltageLevelModeConfig = 0x8138, /// R/W SoftwareClockSync = 0x813C, /// W BoardInfo = 0x8140, /// R AnalogMonitorMode = 0x8144, /// R/W EventSize = 0x814C, /// R FanSpeedControl = 0x8168, /// R/W MemoryBufferAlmostFullLevel = 0x816C, /// R/W RunStartStopDelay = 0x8170, /// R/W BoardFailureStatus = 0x8178, /// R FrontPanelLVDSIONewFeatures = 0x81A0, /// R/W BufferOccupancyGain = 0x81B4, /// R/W ChannelsShutdown = 0x81C0, /// W ExtendedVetoDelay = 0x81C4, /// R/W ReadoutControl = 0xEF00, /// R/W ReadoutStatus = 0xEF04, /// R BoardID = 0xEF08, /// R/W MCSTBaseAddressAndControl = 0xEF0C, /// R/W RelocationAddress = 0xEF10, /// R/W InterruptStatusID = 0xEF14, /// R/W InterruptEventNumber = 0xEF18, /// R/W MaxNumberOfEventsPerBLT = 0xEF1C, /// R/W Scratch = 0xEF20, /// R/W SoftwareReset = 0xEF24, /// W SoftwareClear = 0xEF28 /// W }; ///====== Common for PHA and PSD enum class RegisterDPP : uint32_t { RecordLength = 0x1020, /// R/W InputDynamicRange = 0x1028, /// R/W NumberEventsPerAggregate = 0x1034, /// R/W PreTrigger = 0x1038, /// R/W TriggerThreshold = 0x106C, /// R/W TriggerHoldOffWidth = 0x1074, /// R/W DPPAlgorithmControl = 0x1080, /// R/W ChannelStatus = 0x1088, /// R AMCFirmwareRevision = 0x108C, /// R ChannelDCOffset = 0x1098, /// R/W ChannelADCTemperature = 0x10A8, /// R IndividualSoftwareTrigger = 0x10C0, /// W VetoWidth = 0x10D4, /// R/W BoardConfiguration = 0x8000, /// R/W AggregateOrganization = 0x800C, /// R/W ADCCalibration = 0x809C, /// W ChannelShutdown = 0x80BC, /// W AcquisitionControl = 0x8100, /// R/W AcquisitionStatus = 0x8104, /// R SoftwareTrigger = 0x8108, /// W GlobalTriggerMask = 0x810C, /// R/W FrontPanelTRGOUTEnableMask = 0x8110, /// R/W LVDSIOData = 0x8118, /// R/W FrontPanelIOControl = 0x811C, /// R/W ChannelEnableMask = 0x8120, /// R/W ROCFPGAFirmwareRevision = 0x8124, /// R EventStored = 0x812C, /// R VoltageLevelModeConfig = 0x8138, /// R/W SoftwareClockSync = 0x813C, /// W BoardInfo = 0x8140, /// R AnalogMonitorMode = 0x8144, /// R/W EventSize = 0x814C, /// R TimeBombDowncounter = 0x8158, /// R FanSpeedControl = 0x8168, /// R/W RunStartStopDelay = 0x8170, /// R/W BoardFailureStatus = 0x8178, /// R DisableExternalTrigger = 0x817C, /// R/W TriggerValidationMask = 0x8180, /// R/W, 0x8180 + 4n FrontPanelLVDSIONewFeatures = 0x81A0, /// R/W BufferOccupancyGain = 0x81B4, /// R/W ExtendedVetoDelay = 0x81C4, /// R/W ReadoutControl = 0xEF00, /// R/W ReadoutStatus = 0xEF04, /// R BoardID = 0xEF08, /// R/W MCSTBaseAddressAndControl = 0xEF0C, /// R/W RelocationAddress = 0xEF10, /// R/W InterruptStatusID = 0xEF14, /// R/W InterruptEventNumber = 0xEF18, /// R/W MaxNumberOfEventsPerBLT = 0xEF1C, /// R/W Scratch = 0xEF20, /// R/W SoftwareReset = 0xEF24, /// W SoftwareClear = 0xEF28 /// W }; enum class RegisterPHA : uint32_t { DataFlush = 0x103C, /// W not sure ChannelStopAcquisition = 0x1040, /// R/W not sure RCCR2SmoothingFactor = 0x1054, /// R/W Trigger Filter smoothing, triggerSmoothingFactor InputRiseTime = 0x1058, /// R/W OK TrapezoidRiseTime = 0x105C, /// R/W OK TrapezoidFlatTop = 0x1060, /// R/W OK PeakingTime = 0x1064, /// R/W OK DecayTime = 0x1068, /// R/W OK TriggerThreshold = 0x106C, /// R/W OK RiseTimeValidationWindow = 0x1070, /// R/W OK TriggerHoldOffWidth = 0x1074, /// R/W OK PeakHoldOff = 0x1078, /// R/W OK ShapedTriggerWidth = 0x1084, /// R/W not sure DPPAlgorithmControl2 = 0x10A0, /// R/W OK FineGain = 0x10C4, /// R/W OK }; enum class RegisterPSD : uint32_t { CFDSetting = 0x103C, /// R/W ForcedDataFlush = 0x1040, /// W ChargeZeroSuppressionThreshold = 0x1044, /// R/W ShortGateWidth = 0x1054, /// R/W LongGateWidth = 0x1058, /// R/W GateOffset = 0x105C, /// R/W TriggerThreshold = 0x1060, /// R/W FixedBaseline = 0x1064, /// R/W TriggerLatency = 0x106C, /// R/W ShapedTriggerWidth = 0x1070, /// R/W TriggerHoldOffWidth = 0x1074, /// R/W ThresholdForPSDCut = 0x1078, /// R/W PureGapThreshold = 0x107C, /// R/W DPPAlgorithmControl2 = 0x1084, /// R/W EarlyBaselineFreeze = 0x10D8, /// R/W }; #endif