#include "DigitizerPHA.h" DigitizerPHA::DigitizerPHA(){ DPPType = V1730_DPP_PHA_CODE; } DigitizerPHA::DigitizerPHA(int boardID, int portID, bool verbose){ OpenDigitizer(boardID, portID, true, verbose); } DigitizerPHA::~DigitizerPHA(){ } int DigitizerPHA::ProgramBoard(){ ret = CAEN_DGTZ_Reset(handle); printf("======== program board PHA\n"); ret = CAEN_DGTZ_WriteRegister(handle, Register::DPP::RecordLength_G + 0x7000, 625); ret = CAEN_DGTZ_WriteRegister(handle, Register::DPP::BoardConfiguration, 0x4E8115); //TODO change to write register ret = CAEN_DGTZ_SetAcquisitionMode(handle, CAEN_DGTZ_SW_CONTROLLED); /// software command ret |= CAEN_DGTZ_SetIOLevel(handle, CAEN_DGTZ_IOLevel_NIM); ret |= CAEN_DGTZ_SetExtTriggerInputMode(handle, CAEN_DGTZ_TRGMODE_ACQ_ONLY); ret = CAEN_DGTZ_SetChannelEnableMask(handle, 0xFFFF); //ret = CAEN_DGTZ_SetNumEventsPerAggregate(handle, 0); ret = CAEN_DGTZ_SetRunSynchronizationMode(handle, CAEN_DGTZ_RUN_SYNC_Disabled); if( ret != 0 ) { printf("==== set board error.\n"); return 0;} printf("======== program Channels PHA\n"); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::DecayTime + 0x7000 , 5000 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TrapezoidFlatTop + 0x7000 , 0x62 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TrapezoidRiseTime + 0x7000 , 6 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::PeakingTime + 0x7000 , 6 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::RCCR2SmoothingFactor + 0x7000 , 4 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::InputRiseTime + 0x7000 , 6 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TriggerThreshold + 0x7000 , 1000 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::PeakHoldOff + 0x7000 , 0x3E ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TriggerHoldOffWidth + 0x7000 , 0x3E ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::RiseTimeValidationWindow + 0x7000 , 0x0 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::ChannelDCOffset + 0x7000 , 0xEEEE ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PreTrigger + 0x7000 , 124 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::InputDynamicRange + 0x7000 , 0x0 ); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::NumberEventsPerAggregate_G + 0x7000, 100); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::AggregateOrganization, 0); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::MaxAggregatePerBlockTransfer, 40); ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::DPPAlgorithmControl + 0x7000, 0xe30200f); if( ret != 0 ) { printf("==== set channels error.\n"); return 0;} printf("End of program board and channels\n"); return ret; } void DigitizerPHA::SetSetting(Setting::PHA settingName, float value, int ch){ unsigned int input = 0; switch(settingName){ /// board setting case Setting::PHA::AutoDataFlush_board_bool: input = value; SetBits(Register::DPP::BoardConfiguration, input, 1, 0); break; case Setting::PHA::DualTrace_board_bool: input = value; SetBits(Register::DPP::BoardConfiguration, input, 1, 11); break; case Setting::PHA::AnalogProbe1_board_2bit: input = value; SetBits(Register::DPP::BoardConfiguration, input, 2, 12); break; case Setting::PHA::AnalogProbe2_board_2bit: input = value; SetBits(Register::DPP::BoardConfiguration, input, 2, 14); break; case Setting::PHA::WavefromRecording_board_bool: input = value; SetBits(Register::DPP::BoardConfiguration, input, 1, 16); break; case Setting::PHA::EnableExtra2Word_board_bool: input = value; SetBits(Register::DPP::BoardConfiguration, input, 1, 17); break; case Setting::PHA::EnergyRecording_board_bool: input = value; SetBits(Register::DPP::BoardConfiguration, input, 1, 19); break; case Setting::PHA::VirtualProbe_board_4bit: input = value; SetBits(Register::DPP::BoardConfiguration, input, 1, 20); break; /// DPP Algorithm Control 1 case Setting::PHA::TrapazoidRescaling_5bit: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 5, 0, ch); break; case Setting::PHA::WaveformDecimation_2bit: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 2, 8, ch); break; case Setting::PHA::WaveformDecimationGain_2bit: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 2, 10, ch); break; case Setting::PHA::PeakSampling_2bit: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 2, 12, ch); break; case Setting::PHA::PulsePolarity_bool: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 1, 16, ch); break; case Setting::PHA::TriggerMode_2bit: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 2, 18, ch); break; case Setting::PHA::BaselineSampling_3bit: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 3, 20, ch); break; case Setting::PHA::DisableSelfTrigger_bool: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 1, 24, ch); break; case Setting::PHA::RolloverFlag_bool: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 1, 26, ch); break; case Setting::PHA::PileupFlag_bool: input = value; SetBits(Register::DPP::DPPAlgorithmControl, input, 1, 27, ch); break; /// DPP Algorithm Control 2 case Setting::PHA::LocalShapedTrigger_bool: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 2, ch); break; case Setting::PHA::LocalShapedTriggerMode_2bit: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 0, ch); break; case Setting::PHA::LocalTriggerValidation_bool: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 6, ch); break; case Setting::PHA::LocalTriggerValidationMode_2bit: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 4, ch); break; case Setting::PHA::Extra2WordOption_3bit: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 3, 8, ch); break; case Setting::PHA::VetoSource_2bit: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 14, ch); break; case Setting::PHA::TriggerCounterRateStep_2bit: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 16, ch); break; case Setting::PHA::BaselineCalculationWhenACQOFF_bool: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 18, ch); break; case Setting::PHA::TagCorrelatedEvents_bool: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 19, ch); break; case Setting::PHA::BaselineRestoreOptimization_bool: input = value; SetBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 29, ch); break; /// ACQ control case Setting::PHA::StartStopMode_2bit: input = value; SetBits(Register::DPP::AcquisitionControl, input, 2, 0); break; case Setting::PHA::StartStopACQ_bool: input = value; SetBits(Register::DPP::AcquisitionControl, input, 1, 2); break; case Setting::PHA::PLLClockSource_bool: input = value; SetBits(Register::DPP::AcquisitionControl, input, 1, 6); break; case Setting::PHA::VetoInForTRGOUT_bool: input = value; SetBits(Register::DPP::AcquisitionControl, input, 1, 12); break; /// Global Trigger Mask case Setting::PHA::GlobalTrgMask_8bit: input = value; SetBits(Register::DPP::GlobalTriggerMask, input, 8, 0); break; case Setting::PHA::GlobalTrgMajorityCoincienceWindow_4bit: input = value; SetBits(Register::DPP::GlobalTriggerMask, input, 4, 20); break; case Setting::PHA::GlobalTrgMajorityLevel_3bit: input = value; SetBits(Register::DPP::GlobalTriggerMask, input, 3, 24); break; case Setting::PHA::GlobalTrgExternalTrigger_bool: input = value; SetBits(Register::DPP::GlobalTriggerMask, input, 1, 30); break; case Setting::PHA::GlobalTrgSoftwareTrigger_bool: input = value; SetBits(Register::DPP::GlobalTriggerMask, input, 1, 31); break; /// Front Panel TRG-OUT Mask case Setting::PHA::FrontTRGOUTMask_8bit: input = value; SetBits(Register::DPP::FrontPanelTRGOUTEnableMask, input, 8, 0); break; case Setting::PHA::FrontTRGOUTLogic_2bit: input = value; SetBits(Register::DPP::FrontPanelTRGOUTEnableMask, input, 2, 8); break; case Setting::PHA::FrontTRGOUTMajorityLevel_3bit: input = value; SetBits(Register::DPP::FrontPanelTRGOUTEnableMask, input, 3, 10); break; case Setting::PHA::FrontTRGOUTExternalTrigger_bool: input = value; SetBits(Register::DPP::FrontPanelTRGOUTEnableMask, input, 1, 30); break; case Setting::PHA::FrontTRGOUTSoftwareTrigger_bool: input = value; SetBits(Register::DPP::FrontPanelTRGOUTEnableMask, input, 1, 31); break; /// Front Plane I/O case Setting::PHA::FrontPanelIO_LEMO_bool: input = value; SetBits(Register::DPP::FrontPanelIOControl, input, 1, 0); break; case Setting::PHA::FrontPanelIO_TRGOUT_bool: input = value; SetBits(Register::DPP::FrontPanelIOControl, input, 1, 1); break; case Setting::PHA::FrontPanelIO_TRGINCtrl_bool: input = value; SetBits(Register::DPP::FrontPanelIOControl, input, 1, 10); break; case Setting::PHA::FrontPanelIO_TRGINtoMezzanines_bool: input = value; SetBits(Register::DPP::FrontPanelIOControl, input, 1, 11); break; case Setting::PHA::FrontPanelIO_TRGOUTmode_6bit: input = value; SetBits(Register::DPP::FrontPanelIOControl, input, 6, 14); break; /// Trigger Validation Mask case Setting::PHA::TriggerValidationMask_8bit: input = value; SetBits(Register::DPP::TriggerValidationMask, input, 8, 0); break; case Setting::PHA::TriggerValidationOperation_2bit: input = value; SetBits(Register::DPP::TriggerValidationMask, input, 2, 8); break; case Setting::PHA::TriggerValidationMajority_3bit: input = value; SetBits(Register::DPP::TriggerValidationMask, input, 3, 10); break; case Setting::PHA::TriggerValidationExternalTrigger_bool: input = value; SetBits(Register::DPP::TriggerValidationMask, input, 1, 30); break; case Setting::PHA::TriggerValidationSoftwareTrigger_bool: input = value; SetBits(Register::DPP::TriggerValidationMask, input, 1, 31); break; /// Registers case Setting::PHA::RecordLength_G_ns: input = value / 8 / ch2ns; WriteRegister(Register::DPP::RecordLength_G, input, ch) ; break; case Setting::PHA::PreTriggerLength_ns: input = value / 4 / ch2ns; WriteRegister(Register::DPP::PreTrigger, input, ch) ; break; case Setting::PHA::InputDynamicRange_bool: input = value; WriteRegister(Register::DPP::InputDynamicRange, input, ch) ; break; case Setting::PHA::DCOffset_precentage: input = (1.0 - value) * 0xFFFF; WriteRegister(Register::DPP::ChannelDCOffset, input, ch) ; break; case Setting::PHA::EventPreAggregate_G_max1023: input = value; WriteRegister(Register::DPP::NumberEventsPerAggregate_G, input, ch) ; break; case Setting::PHA::AggregateOrganization_board_3bit: input = value; WriteRegister(Register::DPP::AggregateOrganization , input, ch) ; break; case Setting::PHA::MaxAggregatePreBlockTransfer_board_10bit: input = value; WriteRegister(Register::DPP::MaxAggregatePerBlockTransfer, input, ch) ; break; case Setting::PHA::VetoWidth_ns:{ unsigned int input = 0 ; if( value <= 4 * ch2ns ){ input = 0; }else if( 4 * ch2ns < value && value <= 1000 * ch2ns ){ input = 1; }else if(1000 * ch2ns < value && value <= 262000 * ch2ns){ input = 2; }else{ input = 3; } WriteRegister(Register::DPP::VetoWidth, input, ch) ; break; } case Setting::PHA::TriggerThreshold_LSD: input = value; WriteRegister(Register::DPP::PHA::TriggerThreshold , input, ch); break; case Setting::PHA::TriggerHoldOffWidth_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::TriggerHoldOffWidth , input, ch); break; case Setting::PHA::TriggerSmoothingFactor_5bit: input = value; WriteRegister(Register::DPP::PHA::RCCR2SmoothingFactor , input, ch); break; case Setting::PHA::TriggerOutputWidth_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::ShapedTriggerWidth , input, ch); break; case Setting::PHA::InputRiseTime_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::InputRiseTime , input, ch); break; case Setting::PHA::TrapezoidRiseTime_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::TrapezoidRiseTime, input, ch); break; case Setting::PHA::TrapezoidFlatTop_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::TrapezoidFlatTop, input, ch); break; case Setting::PHA::DecayTime_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::DecayTime, input, ch); break; case Setting::PHA::PeakingTime_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::PeakingTime, input, ch); break; case Setting::PHA::PeakingHoldOff_ns: input = value / 4/ ch2ns; WriteRegister(Register::DPP::PHA::PeakHoldOff, input, ch); break; case Setting::PHA::EnergyFineGain_16bit: input = value; WriteRegister(Register::DPP::PHA::FineGain, input, ch); break; case Setting::PHA::RiseTimeValidationWindow_ns: input = value / ch2ns; WriteRegister(Register::DPP::PHA::RiseTimeValidationWindow, input, ch); break; /// Others case Setting::PHA::FanSpeedControl_bool: input = value; WriteRegister(Register::DPP::FanSpeedControl, input); break; case Setting::PHA::RunStartStopDelay_8bit: input = value; WriteRegister(Register::DPP::RunStartStopDelay, input); break; case Setting::PHA::DisableExternalTrigger_bool: input = value; WriteRegister(Register::DPP::DisableExternalTrigger, input); break; case Setting::PHA::ExtendedVetoDelay_16bit: input = value; WriteRegister(Register::DPP::ExtendedVetoDelay, input); break; case Setting::PHA::AnalogMonitorMode_3bit: input = value; WriteRegister(Register::DPP::AnalogMonitorMode, input); break; case Setting::PHA::BufferOccupancyGain_4bit: input = value; WriteRegister(Register::DPP::BufferOccupancyGain, input); break; } ErrorMsg("PHA-" + std::to_string(settingName) ); } double DigitizerPHA::GetSetting(Setting::PHA settingName, int ch){ double value = 0; unsigned int temp; switch(settingName){ /// board setting case Setting::PHA::AutoDataFlush_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 0); value = temp; break; case Setting::PHA::DecimateWaveForm_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 1); value = temp; break; case Setting::PHA::TriggerPropapation_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 2); value = temp; break; case Setting::PHA::DualTrace_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 11); value = temp; break; case Setting::PHA::AnalogProbe1_board_2bit: temp = ReadBits(Register::DPP::BoardConfiguration, 2, 12); value = temp; break; case Setting::PHA::AnalogProbe2_board_2bit: temp = ReadBits(Register::DPP::BoardConfiguration, 2, 14); value = temp; break; case Setting::PHA::WavefromRecording_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 16); value = temp; break; case Setting::PHA::EnableExtra2Word_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 17); value = temp; break; case Setting::PHA::EnergyRecording_board_bool: temp = ReadBits(Register::DPP::BoardConfiguration, 1, 19); value = temp; break; case Setting::PHA::VirtualProbe_board_4bit: temp = ReadBits(Register::DPP::BoardConfiguration, 4, 20); value = temp; break; /// DPP Algorithm Control 1 case Setting::PHA::TrapazoidRescaling_5bit: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 5, 0, ch); value = temp; break; case Setting::PHA::WaveformDecimation_2bit: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 2, 8, ch); value = temp; break; case Setting::PHA::WaveformDecimationGain_2bit: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 2, 10, ch); value = temp; break; case Setting::PHA::PeakSampling_2bit: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 2, 12, ch); value = pow(4, temp); break; case Setting::PHA::PulsePolarity_bool: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 1, 16, ch); value = temp; break; case Setting::PHA::TriggerMode_2bit: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 2, 18, ch); value = temp; break; case Setting::PHA::BaselineSampling_3bit: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 3, 20, ch); value = pow(4, 1 + temp); break; case Setting::PHA::DisableSelfTrigger_bool: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 1, 24, ch); value = temp; break; case Setting::PHA::RolloverFlag_bool: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 1, 26, ch); value = temp; break; case Setting::PHA::PileupFlag_bool: temp = ReadBits(Register::DPP::DPPAlgorithmControl, 1, 27, ch); value = temp; break; /// DPP Algorithm Control 2 case Setting::PHA::LocalShapedTriggerMode_2bit: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 0, ch); value = temp; break; case Setting::PHA::LocalShapedTrigger_bool: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 2, ch); value = temp; break; case Setting::PHA::LocalTriggerValidationMode_2bit: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 4, ch); value = temp; break; case Setting::PHA::LocalTriggerValidation_bool: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 6, ch); value = temp; break; case Setting::PHA::Extra2WordOption_3bit: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 3, 8, ch); value = temp; break; case Setting::PHA::VetoSource_2bit: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 2, 14, ch); value = temp; break; case Setting::PHA::TriggerCounterRateStep_2bit: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 16, ch); value = temp; break; case Setting::PHA::BaselineCalculationWhenACQOFF_bool: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 18, ch); value = temp; break; case Setting::PHA::TagCorrelatedEvents_bool: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 19, ch); value = temp; break; case Setting::PHA::BaselineRestoreOptimization_bool: temp = ReadBits(Register::DPP::PHA::DPPAlgorithmControl2_G, 1, 29, ch); value = temp; break; /// ACQ control case Setting::PHA::StartStopMode_2bit: temp = ReadBits(Register::DPP::AcquisitionControl, 2, 0); value = temp; break; case Setting::PHA::StartStopACQ_bool: temp = ReadBits(Register::DPP::AcquisitionControl, 1, 2); value = temp; break; case Setting::PHA::PLLClockSource_bool: temp = ReadBits(Register::DPP::AcquisitionControl, 1, 6); value = temp; break; case Setting::PHA::VetoInForTRGOUT_bool: temp = ReadBits(Register::DPP::AcquisitionControl, 1, 12); value = temp; break; /// Global Trigger Mask case Setting::PHA::GlobalTrgMask_8bit: temp = ReadBits(Register::DPP::GlobalTriggerMask, 8, 0); value = temp; break; case Setting::PHA::GlobalTrgMajorityCoincienceWindow_4bit: temp = ReadBits(Register::DPP::GlobalTriggerMask, 4, 20); value = temp; break; case Setting::PHA::GlobalTrgMajorityLevel_3bit: temp = ReadBits(Register::DPP::GlobalTriggerMask, 3, 24); value = temp; break; case Setting::PHA::GlobalTrgExternalTrigger_bool: temp = ReadBits(Register::DPP::GlobalTriggerMask, 1, 30); value = temp; break; case Setting::PHA::GlobalTrgSoftwareTrigger_bool: temp = ReadBits(Register::DPP::GlobalTriggerMask, 1, 31); value = temp; break; /// Front Panel TRG-OUT Mask case Setting::PHA::FrontTRGOUTMask_8bit: temp = ReadBits(Register::DPP::FrontPanelTRGOUTEnableMask, 8, 0); value = temp; break; case Setting::PHA::FrontTRGOUTLogic_2bit: temp = ReadBits(Register::DPP::FrontPanelTRGOUTEnableMask, 2, 8); value = temp; break; case Setting::PHA::FrontTRGOUTMajorityLevel_3bit: temp = ReadBits(Register::DPP::FrontPanelTRGOUTEnableMask, 3, 10); value = temp; break; case Setting::PHA::FrontTRGOUTExternalTrigger_bool: temp = ReadBits(Register::DPP::FrontPanelTRGOUTEnableMask, 1, 30); value = temp; break; case Setting::PHA::FrontTRGOUTSoftwareTrigger_bool: temp = ReadBits(Register::DPP::FrontPanelTRGOUTEnableMask, 1, 31); value = temp; break; /// Front Plane I/O case Setting::PHA::FrontPanelIO_LEMO_bool: temp = ReadBits(Register::DPP::FrontPanelIOControl, 1, 0); value = temp; break; case Setting::PHA::FrontPanelIO_TRGOUT_bool: temp = ReadBits(Register::DPP::FrontPanelIOControl, 1, 1); value = temp; break; case Setting::PHA::FrontPanelIO_TRGINCtrl_bool: temp = ReadBits(Register::DPP::FrontPanelIOControl, 1, 10); value = temp; break; case Setting::PHA::FrontPanelIO_TRGINtoMezzanines_bool: temp = ReadBits(Register::DPP::FrontPanelIOControl, 1, 11); value = temp; break; case Setting::PHA::FrontPanelIO_TRGOUTmode_6bit: temp = ReadBits(Register::DPP::FrontPanelIOControl, 6, 14); value = temp; break; /// Trigger Validation Mask case Setting::PHA::TriggerValidationMask_8bit: temp = ReadBits(Register::DPP::TriggerValidationMask, 8, 0); value = temp; break; case Setting::PHA::TriggerValidationOperation_2bit: temp = ReadBits(Register::DPP::TriggerValidationMask, 2, 8); value = temp; break; case Setting::PHA::TriggerValidationMajority_3bit: temp = ReadBits(Register::DPP::TriggerValidationMask, 3, 10); value = temp; break; case Setting::PHA::TriggerValidationExternalTrigger_bool: temp = ReadBits(Register::DPP::TriggerValidationMask, 1, 30); value = temp; break; case Setting::PHA::TriggerValidationSoftwareTrigger_bool: temp = ReadBits(Register::DPP::TriggerValidationMask, 1, 31); value = temp; break; /// Registers case Setting::PHA::RecordLength_G_ns: temp = ReadRegister(Register::DPP::RecordLength_G , ch); value = temp * 8 * ch2ns;break; case Setting::PHA::PreTriggerLength_ns: temp = ReadRegister(Register::DPP::PreTrigger , ch); value = temp * 4 * ch2ns;break; case Setting::PHA::InputDynamicRange_bool: temp = ReadRegister(Register::DPP::InputDynamicRange , ch); value = temp;break; case Setting::PHA::DCOffset_precentage: temp = ReadRegister(Register::DPP::ChannelDCOffset , ch); value = 1.0 - temp * 1.0 / 0xFFFF ;break; case Setting::PHA::EventPreAggregate_G_max1023: temp = ReadRegister(Register::DPP::NumberEventsPerAggregate_G , ch); value = temp; break; case Setting::PHA::VetoWidth_ns: { temp = ReadRegister(Register::DPP::VetoWidth , ch); switch( temp) { case 0 : value = 4 * ch2ns; break; ///ns case 1 : value = 1000 * ch2ns; break; ///ns case 2 : value = 262000 * ch2ns; break; ///ns case 3 : value = 66000000 * ch2ns; break; ///ns default : value = temp; break; /// bit } break; } case Setting::PHA::AggregateOrganization_board_3bit:{ temp = ReadRegister(Register::DPP::AggregateOrganization , ch); value = ((temp & 0x007) < 2 ? 0 : (int)pow(2, temp & 7)); break; } case Setting::PHA::MaxAggregatePreBlockTransfer_board_10bit: temp = ReadRegister(Register::DPP::MaxAggregatePerBlockTransfer , ch); value = temp; break; case Setting::PHA::TriggerThreshold_LSD: temp = ReadRegister(Register::DPP::PHA::TriggerThreshold , ch); value = temp; break; case Setting::PHA::TriggerHoldOffWidth_ns: temp = ReadRegister(Register::DPP::PHA::TriggerHoldOffWidth , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::TriggerSmoothingFactor_5bit: temp = ReadRegister(Register::DPP::PHA::RCCR2SmoothingFactor , ch); value = (temp & 0x1f) * 2 * ch2ns;break; case Setting::PHA::TriggerOutputWidth_ns: temp = ReadRegister(Register::DPP::PHA::ShapedTriggerWidth , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::InputRiseTime_ns: temp = ReadRegister(Register::DPP::PHA::InputRiseTime , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::TrapezoidRiseTime_ns: temp = ReadRegister(Register::DPP::PHA::TrapezoidRiseTime , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::TrapezoidFlatTop_ns: temp = ReadRegister(Register::DPP::PHA::TrapezoidFlatTop , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::DecayTime_ns: temp = ReadRegister(Register::DPP::PHA::DecayTime , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::PeakingTime_ns: temp = ReadRegister(Register::DPP::PHA::PeakingTime , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::PeakingHoldOff_ns: temp = ReadRegister(Register::DPP::PHA::PeakHoldOff , ch); value = temp * 4 * ch2ns; break; case Setting::PHA::EnergyFineGain_16bit: temp = ReadRegister(Register::DPP::PHA::FineGain , ch); value = temp; break; case Setting::PHA::RiseTimeValidationWindow_ns: temp = ReadRegister(Register::DPP::PHA::RiseTimeValidationWindow , ch); value = temp * ch2ns; break; /// Others case Setting::PHA::FanSpeedControl_bool: temp = ReadRegister(Register::DPP::FanSpeedControl); value = temp & 0x8; break; case Setting::PHA::RunStartStopDelay_8bit: temp = ReadRegister(Register::DPP::RunStartStopDelay); value = temp & 0xFF; break; case Setting::PHA::DisableExternalTrigger_bool: temp = ReadRegister(Register::DPP::DisableExternalTrigger); value = temp & 0x1; break; case Setting::PHA::ExtendedVetoDelay_16bit: temp = ReadRegister(Register::DPP::ExtendedVetoDelay); value = temp & 0xffff; break; case Setting::PHA::AnalogMonitorMode_3bit: temp = ReadRegister(Register::DPP::AnalogMonitorMode); value = temp & 0x7; break; case Setting::PHA::BufferOccupancyGain_4bit: temp = ReadRegister(Register::DPP::BufferOccupancyGain); value = temp & 0xf; break; /// AMC Firmware Revisiion case Setting::PHA::AMCFirmwareNumber_readOnly_8bit: temp = ReadBits(Register::DPP::AMCFirmwareRevision, 7, 0); value = temp; break; case Setting::PHA::AMCDPPcode_readOnly_8bit: temp = ReadBits(Register::DPP::AMCFirmwareRevision, 8, 8); value = temp; break; case Setting::PHA::AMCBuildDay_readOnly_8bit: temp = ReadBits(Register::DPP::AMCFirmwareRevision, 8, 16); value = temp; break; case Setting::PHA::AMCBuildMonth_readOnly_4bits: temp = ReadBits(Register::DPP::AMCFirmwareRevision, 4, 24); value = temp; break; case Setting::PHA::AMCBuildYear_readOnly_4bits: temp = ReadBits(Register::DPP::AMCFirmwareRevision, 4, 28); value = temp; break; /// ACQ Status case Setting::PHA::ACQStatus_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 2); value = temp; break; case Setting::PHA::ACQEventReady_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 3); value = temp; break; case Setting::PHA::ACQEventFull_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 4); value = temp; break; case Setting::PHA::ACQClockSource_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 5); value = temp; break; case Setting::PHA::ACQPLLLock_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 7); value = temp; break; case Setting::PHA::ACQBoardReady_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 8); value = temp; break; case Setting::PHA::ACQ_S_IN_Statue_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 15); value = temp; break; case Setting::PHA::ACQ_TRGIN_Status_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 16); value = temp; break; case Setting::PHA::ACQChannelShutDownStatus_readOnly_bool: temp = ReadBits(Register::DPP::AcquisitionStatus, 1, 19); value = temp; break; case Setting::PHA::ACQTenmperatureStatus_readOnly_4bit: temp = ReadBits(Register::DPP::AcquisitionStatus, 4, 20); value = temp; break; } return value; } void DigitizerPHA::AutoSetTrapezoidRescalingAndFindGate(double gain, int ch){ int startCh = 0; int endCh = MaxNChannels; if( ch >= 0 ){ startCh = ch; endCh = ch; } for( int i = startCh ; i <= endCh; i++){ double riseTime = ReadRegister(Register::DPP::PHA::TrapezoidRiseTime, i) * 4 * ch2ns; double flatTop = ReadRegister(Register::DPP::PHA::TrapezoidFlatTop, i) * 4 * ch2ns; unsigned int shift = (unsigned int ) ( log(riseTime * flatTop ) / log(2.0)) ; SetTrapezoidRescaling(shift, i); double haha = 0xFFFF * gain * (pow(2, shift) / riseTime / flatTop); unsigned int fineGain = (unsigned int) (haha); if( fineGain > 0xFFFF ){ SetEnergyFineGain(0xFFFF, i); }else{ SetEnergyFineGain(fineGain, i); } } ErrorMsg("PHA-AutoSetTrapezoidRescalingAndFindGate"); } void DigitizerPHA::PrintBoardConfiguration(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::BoardConfiguration, "Board Configuration"); printf(" Bit[ 0] = %d = Auto Data Flush \n", value & 0x1); printf(" Bit[ 1] = %d = Decimated waveform \n", (value >> 1) & 0x1 ); printf(" Bit[ 2] = %d = Trigger propagation \n", (value >> 2) & 0x1 ); printf(" Bit[ 3:10] = %d = must be 001 0001 0 = 22 \n", (value >> 3) & 0xFF ); printf(" Bit[ 11] = %d = Dual Trace \n", (value >> 11) & 0x1 ); printf(" Bit[12:13] = %d = Analog probe 1 : ",((value >> 12) & 0x3 )); switch ( ((value >> 12) & 0x3 ) ){ case 0 : printf("input\n"); break; case 1 : printf("RC-CR (1st derivative)\n");break; case 2 : printf("RC-CR2 (2nd derivative)\n"); break; case 3 : printf("Trapezoid \n"); break; } printf(" Bit[14:15] = %d = Analog probe 2 : ", ((value >> 14) & 0x3 )); switch ( ((value >> 14) & 0x3 ) ){ case 0 : printf("input\n"); break; case 1 : printf("Threshold\n"); break; case 2 : printf("Trapezoid - Baseline\n"); break; case 3 : printf("baseline.\n"); break; } printf(" Bit[ 16] = %d = WaveForm Recording \n",((value >> 16) & 0x1 ) ); printf(" Bit[ 17] = %d = Extras 2 word enable \n", ((value >> 17) & 0x1 )); printf(" Bit[ 18] = %d = Record Time Stamp \n", ((value >> 18) & 0x1 )); printf(" Bit[ 19] = %d = Record Energy \n", ((value >> 19) & 0x1 )); printf(" Bit[20:23] = %d = Digital Virtual probe 1 : ", ((value >> 20) & 0x7 )); switch (((value >> 20) & 0xF )) { case 0: printf("Peaking, shows where the energy is calculated; \n"); break; case 1: printf("”Armed”, digital input showing where the RC‐CR2 crosses the Threshold\n"); break; case 2: printf("”Peak Run”, starts with the trigger and last for the whole event\n");break; case 3: printf("”Pile‐up”, shows where a pile‐up event occurred\n");break; case 4: printf("”Peaking”, shows where the energy is calculated\n");break; case 5: printf("”TRG Validation Win”, digital input showing the trigger validation acceptance window TVAW\n");break; case 6: printf("”Baseline freeze”, shows where the algorithm stops calculating the baseline and its value is frozen\n");break; case 7: printf("”TRG Holdoff”, shows the trigger hold‐off parameter\n");break; case 8: printf("”TRG Validation”, shows the trigger validation signal TRG_VAL \n");break; case 9: printf("”Acq Busy”, this is 1 when the board is busy (saturated input signal or full memory board) or there is a veto\n");break; case 10: printf("”Zero Cross. Win.”, shows the RT Discrimination Width\n");break; case 11: printf("”Ext TRG”, shows the external trigger, when available\n");break; case 12: printf("”Busy”, shows when the memory board is full.\n");break; } printf(" Bit[26:28] = %d = Digital Virtual probe 2 : ", ((value >> 26) & 0x7 )); if( ((value >> 26) & 0x7 ) == 0 ) { printf("Trigger\n"); }else{ printf("Reserved\n"); } } void DigitizerPHA::PrintACQControl(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::AcquisitionControl, "ACQ COntrol"); ///==== Start Stop Mode printf(" Bit[1:0] = %d = Start/Stop Mode (", value & 0x3); switch (value & 0x3){ case 0 : printf("Software controlled)\n"); break; case 1 : printf("S-IN controlled)\n"); break; case 2 : printf("1st trigger controlled)\n"); break; case 3 : printf("LVDS controlled)\n"); break; } ///==== ACQ Start/Arm printf(" Bit[ 2] = %d = Start/Arm (%s)\n", value & 0x4, (value & 0x4) == 0 ? "STOP" : "RUN" ); printf(" Bit[ 6] = %d = PLL Ref. Clock (%s)\n", value & 0x40, (value & 0x40) == 0 ? "Internal" : "External" ); printf(" Bit[ 8] = %d = LVDS I/O Busy Enable (%s)\n", value & 0x100, (value & 0x100) == 0 ? "Disabled" : "Enabled" ); printf(" Bit[ 8] = %d = LVDS I/O Veto Enable (%s)\n", value & 0x200, (value & 0x200) == 0 ? "Disabled" : "Enabled" ); printf(" Bit[ 12] = %d = Veto-in as veto for TRG-OUT (%s)\n", value & 0x1000, (value & 0x1000) == 0 ? "not used" : "used" ); } void DigitizerPHA::PrintGlobalTriggerMask(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::GlobalTriggerMask, "Global Trigger Mask"); printf(" Bit[ 7:0] = 0x%x = Enabled Paired Channel\n", value & 0xff ); printf(" Bit[23:20] = %.0f ns = Majority Coincidence Window\n", (( value >> 20 ) & 0xf) * 4 * ch2ns ); printf(" Bit[26:24] = %d = Majority Level\n", (( value >> 24 ) & 0x7) ); printf(" Bit[ 29] = %d = LVDS Trigger(%s)\n", (( value >> 29 ) & 0x1), (( value >> 29 ) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 30] = %d = External Trigger(%s)\n", (( value >> 30 ) & 0x1), (( value >> 30 ) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 31] = %d = Software Trigger(%s)\n", (( value >> 31 ) & 0x1), (( value >> 31 ) & 0x1) == 0 ? "disabled" : "enabled" ); } void DigitizerPHA::PrintFrontPanelTRIGOUTEnableMask(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::FrontPanelTRGOUTEnableMask, "Front Panel TRG-OUT Mask"); printf(" Bit[ 7:0] = 0x%x = Enabled Paired Channel\n", value & 0xff ); printf(" Bit[ 9:8] = %d = TRG-OUT Logic (", (value >> 8) & 0x3 ); switch ( ( value>>8) & 0x3 ){ case 0 : printf("OR)\n"); break; case 1 : printf("AND)\n"); break; case 2 : printf("MAjority)\n"); break; } printf(" Bit[12:10] = %d = Majority Level\n", (value >> 10) & 0x7 ); printf(" Bit[ 29] = %d = LVDS Trigger(%s)\n", (( value >> 29 ) & 0x1), (( value >> 29 ) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 30] = %d = External Trigger(%s)\n", (( value >> 30 ) & 0x1), (( value >> 30 ) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 31] = %d = Software Trigger(%s)\n", (( value >> 31 ) & 0x1), (( value >> 31 ) & 0x1) == 0 ? "disabled" : "enabled" ); } void DigitizerPHA::PrintFrontPanelIOControl(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::FrontPanelIOControl, "Front Panel I/O Control"); printf(" Bit[ 0] = %d = LEMO I/O (%s)\n", value & 0x1, (value & 0x1) == 0 ? "NIM" : "TTL" ); printf(" Bit[ 1] = %d = TRG-OUT (%s)\n", (value >> 1) & 0x1, ((value >> 1) & 0x1) == 0 ? "enabled" : "high impedance" ); printf(" Bit[ 2] = %d = LVDS I/O [3:0] (%s)\n", (value >> 2) & 0x1, ((value >> 2) & 0x1) == 0 ? "input" : "output" ); printf(" Bit[ 3] = %d = LVDS I/O [7:4] (%s)\n", (value >> 3) & 0x1, ((value >> 3) & 0x1) == 0 ? "input" : "output" ); printf(" Bit[ 4] = %d = LVDS I/O [11:8] (%s)\n", (value >> 4) & 0x1, ((value >> 4) & 0x1) == 0 ? "input" : "output" ); printf(" Bit[ 5] = %d = LVDS I/O [15:12] (%s)\n", (value >> 5) & 0x1, ((value >> 5) & 0x1) == 0 ? "input" : "output" ); printf(" Bit[ 7:6] = %d = LVDS I/O Signal Config (", (value >> 6) & 0x3); switch ((value >> 6) & 0x3){ case 0 : printf("general pupose)\n"); break; case 1 : printf("programmed)\n"); break; case 2 : printf("pattern mode)\n"); break; } printf(" Bit[ 8] = %d = LVDS I/O feature (%s)\n", (value >> 8) & 0x1, ((value >> 8) & 0x1) == 0? "old" : "new" ); printf(" Bit[ 9] = %d = LVDS I/O Latch Mode (%s)\n", (value >> 9) & 0x1, ((value >> 9) & 0x1) == 0? "global trigger" : "external trigger" ); printf(" Bit[ 10] = %d = TRG-IN control (%s)\n", (value >> 10) & 0x1, ((value >> 10) & 0x1) == 0? "trigger sync with the edge of TRG-IN" : "triger sync with whole TRG-IN"); printf(" Bit[ 11] = %d = TRG-IN to Mezzanines (%s)\n", (value >> 11) & 0x1, ((value >> 11) & 0x1) == 0? "by motherboard" : "directly to mezzanine"); printf(" Bit[ 14] = %d = Force TRG-OUT(%s)\n", (value >> 14) & 0x1, ((value >> 14) & 0x1) == 0? "0" : "1"); printf(" Bit[ 15] = %d = TRG-OUT mode(%s)\n", (value >> 15) & 0x1, ((value >> 15) & 0x1) == 0? "internal" : "Forced"); printf(" Bit[17:16] = %d = TRG-OUT mode(", (value >> 16) & 0x3); switch ((value >> 16) & 0x3) { case 0 : printf("Trigger)\n"); break; case 1 : printf("Motherboard Probe)\n"); break; case 2 : printf("Channel Probe)\n"); break; case 3 : printf("S-IN)\n"); break; } printf(" Bit[19:18] = %d = Motherboard Probe(", (value >> 18) & 0x3); switch ((value >> 18) & 0x3) { case 0 : printf("RUN)\n"); break; case 1 : printf("Clock)\n"); break; case 2 : printf("Clock Phase)\n"); break; case 3 : printf("BUSY/UNLOCK)\n"); break; } printf(" Bit[22:21] = %d = Patten Configure(%s)", (value >> 21) & 0x3, ((value >> 21) & 0x3) == 0 ? "default" : "Reserved"); } void DigitizerPHA::PrintTriggerValidationMask(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::TriggerValidationMask, "Trigger Validation Mask"); printf(" Bit[ 7:0] = 0x%x = Enabled Paired Channel\n", value & 0xff ); printf(" Bit[ 9:8] = %d = Operation (\n", (value >> 8) & 0x3 ); switch ( (value >> 8) & 0x3 ) { case 0 : printf("OR)\n"); break; case 1 : printf("AND)\n"); break; case 2 : printf("Majority)\n"); break; case 3 : printf("Reserved)\n"); break; } printf(" Bit[12:10] = %d = Majority Level\n", (value >> 10) & 0x7 ); printf(" Bit[ 28] = %d = LVDS I/O Global Trigger(%s)\n", (value >> 28) & 0x1, ((value >> 28) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 29] = %d = LVDS I/O individual Trigger(%s)\n", (value >> 29) & 0x1, ((value >> 29) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 30] = %d = External Trigger(%s)\n", (value >> 30) & 0x1, ((value >> 30) & 0x1) == 0 ? "disabled" : "enabled" ); printf(" Bit[ 31] = %d = Software Trigger(%s)\n", (value >> 31) & 0x1, ((value >> 31) & 0x1) == 0 ? "disabled" : "enabled" ); } void DigitizerPHA::PrintBoardInfoRegister(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::BoardInfo, "Board Info"); printf(" Bit[ 7:0] = %d = Digitizer Family Code ", value & 0xff ); switch ( value & 0xff ) { case 0x0E : printf("( 725 family )\n"); break; case 0x0B : printf("( 730 family )\n"); break; } printf(" Bit[ 15:8] = %d = Channel Memory Code ", (value >> 8 ) & 0xff ); switch ( (value >> 8 )& 0xff ) { case 0x01 : printf("( 640 kSample per channel)\n"); break; case 0x08 : printf("( 5.12 MSample per channel)\n"); break; } printf(" Bit[23:16] = %d = Channel Number ", (value >> 16 ) & 0xff ); switch ( (value >> 16 )& 0xff ) { case 0x10 : printf("( 16 Channel )\n"); break; case 0x08 : printf("( 8 Channel )\n"); break; } } void DigitizerPHA::PrintBoardFailureState(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::BoardFailureStatus, "Board Failure State"); printf(" Bit[4] = %d = PLL Lock Loss (%s)\n", (value >> 4) & 0x1, ( (value >> 4) & 0x1 ) == 0 ? "no error" : "Lock Loss"); printf(" Bit[5] = %d = Temperature Failure (%s)\n", (value >> 5) & 0x1, ( (value >> 5) & 0x1 ) == 0 ? "no error" : "over heat"); printf(" Bit[6] = %d = ADC Power Down (%s)\n", (value >> 6) & 0x1, ( (value >> 6) & 0x1 ) == 0 ? "no error" : "down"); } void DigitizerPHA::PrintReadoutControl(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::ReadoutControl, "Readout Control"); printf(" Bit[2:0] = %d = VME Interrupt Level %s\n", value & 0x3, ( value & 0x3 ) == 0 ? "(disabled)" : ""); printf(" Bit[ 3] = %d = Optical Link Interrupt (%s)\n", (value >> 3) & 0x1, ( (value >> 3) & 0x1 ) == 0 ? "disabled" : "enabled"); printf(" Bit[ 4] = %d = VME Bus Error / Event Aligned Readout (%s)\n", (value >> 4) & 0x1, ((value >> 4) & 0x1) == 0 ? "disabled" : "enabled") ; printf(" Bit[ 5] = %d = VME Align64 Mode (%s)\n", (value >> 5) & 0x1, ((value >> 5) & 0x1) == 0 ? "disabled" : "enabled") ; printf(" Bit[ 6] = %d = VME Base Address Relocation (%s)\n", (value >> 6) & 0x1, ((value >> 6) & 0x1) == 0 ? "disabled" : "enabled") ; printf(" Bit[ 7] = %d = Interrupt Release Mode (%s)\n", (value >> 7) & 0x1, ((value >> 7) & 0x1) == 0 ? "Release On Register Access" : "Release On Acknowledge") ; printf(" Bit[ 8] = %d = Extended Block Transfer Space (%s)\n", (value >> 8) & 0x1, ((value >> 8) & 0x1) == 0 ? "Release On Register Access" : "Release On Acknowledge") ; } void DigitizerPHA::PrintReadoutStatu(){ if( !isConnected ) return; uint32_t value = PrintRegister(Register::DPP::ReadoutStatus, "Readout Status"); printf(" Bit[0] = %d = Event Ready (%s)\n", value & 0x1, (value & 0x1) == 0? "no date" : "ready"); printf(" Bit[2] = %d = Bus Error (%s)\n", (value >> 2) & 0x1, ((value >> 2) & 0x1) == 0? "no error" : "error occurred"); printf(" Bit[3] = %d = VME FIFO Flag (%s)\n", (value >> 3) & 0x1, ((value >> 3) & 0x1) == 0? "not empty" : "empty"); } void DigitizerPHA::PrintChannelSettingFromDigitizer(int ch){ if( !isConnected ) return; printf("\e[33m================================================\n"); printf("================ Setting for channel %d \n", ch); printf("================================================\e[0m\n"); ///DPP algorithm Control uint32_t * value = new uint32_t[NChannel]; CAEN_DGTZ_ReadRegister(handle, Register::DPP::DPPAlgorithmControl + (ch << 8), value); printf(" 32 28 24 20 16 12 8 4 0\n"); printf(" | | | | | | | | |\n"); cout <<" DPP algorithm Control : 0b" << bitset<32>(value[0]); printf(" = 0x%x\n", value[0]); int trapRescaling = int(value[0]) & 0x1f ; int polarity = int(value[0] >> 16) & 0x1; /// in bit[16] int baseline = int(value[0] >> 20) & 0x7; /// in bit[22:20] int NsPeak = int(value[0] >> 12) & 0x3; /// in bit[13:12] int rollOver = int(value[0] >> 26) & 0x1; int pileUp = int(value[0] >> 27) & 0x1; ///DPP algorithm Control 2 CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::DPPAlgorithmControl2_G + (ch << 8), value); cout <<" DPP algorithm Control 2: 0b" << bitset<32>(value[0]) ; printf(" = 0x%x\n", value[0]); int extras2WordOption = int(value[0] >> 8) & 0x3; string extra2WordOptStr = ""; switch (extras2WordOption){ case 0 : extra2WordOptStr = "[0:15] Baseline *4 [16:31] Extended Time Stamp"; break; case 2 : extra2WordOptStr = "[0:9] Fine Time Stamp [10:15] Reserved [16:31] Extended Time Stamp"; break; case 4 : extra2WordOptStr = "[0:15] Total Trigger Counter [16:31] Lost Trigger Counter"; break; case 5 : extra2WordOptStr = "[0:15] Event After the Zero Crossing [16:31] Event Before the Zero Crossing"; break; default: extra2WordOptStr = "Reserved"; break; } printf(" ch2ns : %.0f ns\n", ch2ns); printf("==========----- input \n"); CAEN_DGTZ_ReadRegister(handle, Register::DPP::RecordLength_G + (ch << 8), value); printf("%24s %5d samples = %5.0f ns \n", "Record Length", ((value[0] * 8) & MaxRecordLength), ((value[0] * 8) & MaxRecordLength) * ch2ns); ///Record length CAEN_DGTZ_ReadRegister(handle, Register::DPP::PreTrigger + (ch << 8), value); printf("%24s %5d samples = %5.0f ns \n", "Pre-tigger", value[0] * 4, value[0] * 4 * ch2ns); ///Pre-trigger printf("%24s %5.0f samples, DPP-[20:22]\n", "baseline mean", pow(4, 1 + baseline)); ///Ns baseline CAEN_DGTZ_ReadRegister(handle, Register::DPP::ChannelDCOffset + (ch << 8), value); printf("%24s %.2f %% \n", "DC offset", 100.0 - value[0] * 100./ 0xFFFF); ///DC offset CAEN_DGTZ_ReadRegister(handle, Register::DPP::InputDynamicRange + (ch << 8), value); printf("%24s %.1f Vpp \n", "input Dynamic", value[0] == 0 ? 2 : 0.5); ///InputDynamic printf("%24s %s, DPP-[16]\n", "polarity", polarity == 0 ? "Positive" : "negative"); ///Polarity printf("==========----- discriminator \n"); CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::TriggerThreshold + (ch << 8), value); printf("%24s %4d LSB\n", "Threshold", value[0]); ///Threshold CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::TriggerHoldOffWidth + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "trigger hold off", value[0], value[0] * 4 * ch2ns); ///Trigger Hold off CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::RCCR2SmoothingFactor + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Fast Dis. smoothing", (value[0] & 0x1f) * 2, (value[0] & 0x1f) * 2 * ch2ns ); ///Fast Discriminator smoothing CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::ShapedTriggerWidth + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Fast Dis. output width", value[0], value[0] * 4 * ch2ns); ///Fast Dis. output width CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::InputRiseTime + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Input rise time ", value[0], value[0] * 4 * ch2ns); ///Input rise time printf("==========----- Trapezoid \n"); CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::TrapezoidRiseTime + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Trap. rise time", value[0], value[0] * 4 * ch2ns); ///Trap. rise time, 2 for 1 ch to 2ns int riseTime = value[0] * 4 * ch2ns; CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::TrapezoidFlatTop + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Trap. flat time", value[0], value[0] * 4 * ch2ns); ///Trap. flat time int flatTopTime = value[0] * 4 * ch2ns; double shift = log(riseTime * flatTopTime ) / log(2) - 2; printf("%24s %4d bit =? %.1f = Ceil( Log(rise [ns] x decay [ns])/Log(2) ), DPP-[0:5]\n", "Trap. Rescaling", trapRescaling, shift ); ///Trap. Rescaling Factor CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::DecayTime + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Decay time", value[0], value[0] * 4 * ch2ns); ///Trap. pole zero CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::PeakingTime + (ch << 8), value); printf("%24s %4d samples, %5.0f ns = %.2f %% of FlatTop\n", "Peaking time", value[0], value[0] * 4 * ch2ns, value[0] * 400. * ch2ns / flatTopTime ); ///Peaking time CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::PeakHoldOff + (ch << 8), value); printf("%24s %4d samples, %5.0f ns \n", "Peak hole off", value[0], value[0] * 4 *ch2ns ); ///Peak hold off printf("%24s %4.0f samples, DPP-[12:13]\n", "Peak mean", pow(4, NsPeak)); ///Ns peak printf("==========----- Other \n"); CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::FineGain + (ch << 8), value); printf("%24s %d = 0x%x\n", "Energy fine gain", value[0], value[0]); ///Energy fine gain CAEN_DGTZ_ReadRegister(handle, Register::DPP::ChannelADCTemperature + (ch << 8), value); printf("%24s %d C\n", "Temperature", value[0]); ///Temperature CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::RiseTimeValidationWindow + (ch << 8), value); printf("%24s %.0f ns \n", "RiseTime Vaild Win.", value[0] * ch2ns); CAEN_DGTZ_ReadRegister(handle, Register::DPP::PHA::ChannelStopAcquisition + (ch << 8), value); printf("%24s %d = %s \n", "Stop Acq bit", value[0] & 1 , (value[0] & 1 ) == 0 ? "Run" : "Stop"); CAEN_DGTZ_ReadRegister(handle, Register::DPP::ChannelStatus + (ch << 8), value); printf("%24s 0x%x \n", "Status bit", (value[0] & 0xff) ); CAEN_DGTZ_ReadRegister(handle, Register::DPP::AMCFirmwareRevision + (ch << 8), value); printf("%24s 0x%x \n", "AMC firmware rev.", value[0] ); CAEN_DGTZ_ReadRegister(handle, Register::DPP::VetoWidth + (ch << 8), value); printf("%24s 0x%x \n", "VetoWidth bit", value[0] ); printf("%24s %d = %s\n", "RollOverFlag, DPP-[26]", rollOver, rollOver ? "enable" : "disable" ); printf("%24s %d = %s\n", "Pile-upFlag, DPP-[27]", pileUp, pileUp ? "enable" : "disable" ); printf("%24s %d, %s \n", "Extra2 opt, DPP2-[8:10]", extras2WordOption, extra2WordOptStr.c_str()); printf("========= events storage and transfer\n"); CAEN_DGTZ_ReadRegister(handle, Register::DPP::NumberEventsPerAggregate_G + (ch << 8), value); printf("%24s %d \n", "Event Aggregate", value[0] & 0x3FF); CAEN_DGTZ_ReadRegister(handle, Register::DPP::AggregateOrganization, value); printf("%24s %d \n", "Buffer Division", ((value[0] & 0x007) < 2 ? 0 : (int)pow(2, value[0] & 7))); CAEN_DGTZ_ReadRegister(handle, Register::DPP::MaxAggregatePerBlockTransfer , value); printf("%24s %d \n", "Num of Agg. / ReadData", value[0] & 0x1FF); printf("========================================= end of ch-%d\n", ch); }