#ifndef REGISTERADDRESS_H
#define REGISTERADDRESS_H

///======= 
/// All 0x1XXX registers are either indiviual or Group
/// Indiviual register are all independence
/// Group register, 2m and 2m+1 channels setting are shared. and the name will have _G as prefix 
/// Most 0x8XXX registers are common, which share for all channel

#define GET_NAME(address) #address  /// this give out the name, printf("%s", GET_NAME(Register::EventReadOutBuffer));

namespace Register {  
  
  const uint32_t EventReadOutBuffer      = 0x0000;  /// R
  
  ///========== Channel or Group
  const uint32_t ChannelDummy32                = 0x1024;  /// R/W
  const uint32_t InputDynamicRange             = 0x1028;  /// R/W
  const uint32_t ChannelPulseWidth             = 0x1070;  /// R/W
  const uint32_t ChannelTriggerThreshold       = 0x1080;  /// R/W
  const uint32_t CoupleSelfTriggerLogic_G      = 0x1084;  /// R/W 
  const uint32_t ChannelStatus_R               = 0x1088;  /// R
  const uint32_t AMCFirmwareRevision_          = 0x108C;  /// R
  const uint32_t ChannelDCOffset               = 0x1098;  /// R/W
  const uint32_t ChannelADCTemperature_R       = 0x10A8;  /// R
  const uint32_t ChannelSelfTriggerRateMeter_R = 0x10EC;  /// R
    
  ///========== Board
  const uint32_t BoardConfiguration           = 0x8000;  /// R/W
  const uint32_t BufferOrganization           = 0x800C;  /// R/W
  const uint32_t CustomSize                   = 0x8020;  /// R/W
  const uint32_t ADCCalibration_W             = 0x809C;  ///   W
  const uint32_t AcquisitionControl           = 0x8100;  /// R/W
  const uint32_t AcquisitionStatus_R          = 0x8104;  /// R
  const uint32_t SoftwareTrigger_W            = 0x8108;  ///   W
  const uint32_t GlobalTriggerMask            = 0x810C;  /// R/W
  const uint32_t FrontPanelTRGOUTEnableMask   = 0x8110;  /// R/W
  const uint32_t PostTrigger                  = 0x8114;  /// R/W
  const uint32_t LVDSIOData                   = 0x8118;  /// R/W
  const uint32_t FrontPanelIOControl          = 0x811C;  /// R/W
  const uint32_t ChannelEnableMask            = 0x8120;  /// R/W
  const uint32_t ROCFPGAFirmwareRevision_R    = 0x8124;  /// R
  const uint32_t EventStored_R                = 0x812C;  /// R
  const uint32_t VoltageLevelModeConfig       = 0x8138;  /// R/W
  const uint32_t SoftwareClockSync_W          = 0x813C;  ///   W 
  const uint32_t BoardInfo_R                  = 0x8140;  /// R
  const uint32_t AnalogMonitorMode            = 0x8144;  /// R/W
  const uint32_t EventSize_R                  = 0x814C;  /// R
  const uint32_t FanSpeedControl              = 0x8168;  /// R/W
  const uint32_t MemoryBufferAlmostFullLevel  = 0x816C;  /// R/W
  const uint32_t RunStartStopDelay            = 0x8170;  /// R/W
  const uint32_t BoardFailureStatus_R         = 0x8178;  /// R
  const uint32_t FrontPanelLVDSIONewFeatures  = 0x81A0;  /// R/W
  const uint32_t BufferOccupancyGain          = 0x81B4;  /// R/W
  const uint32_t ChannelsShutdown_W           = 0x81C0;  ///   W 
  const uint32_t ExtendedVetoDelay            = 0x81C4;  /// R/W
  const uint32_t ReadoutControl               = 0xEF00;  /// R/W
  const uint32_t ReadoutStatus_R              = 0xEF04;  /// R
  const uint32_t BoardID                      = 0xEF08;  /// R/W
  const uint32_t MCSTBaseAddressAndControl    = 0xEF0C;  /// R/W
  const uint32_t RelocationAddress            = 0xEF10;  /// R/W
  const uint32_t InterruptStatusID            = 0xEF14;  /// R/W
  const uint32_t InterruptEventNumber         = 0xEF18;  /// R/W
  const uint32_t MaxAggregatePerBlockTransfer = 0xEF1C;  /// R/W
  const uint32_t Scratch                      = 0xEF20;  /// R/W
  const uint32_t SoftwareReset_W              = 0xEF24;  ///   W
  const uint32_t SoftwareClear_W              = 0xEF28;  ///   W  

  ///====== Common for PHA and PSD
  namespace DPP {
    
    const uint32_t RecordLength_G              = 0x1020; /// R/W
    const uint32_t InputDynamicRange           = 0x1028; /// R/W
    const uint32_t NumberEventsPerAggregate_G  = 0x1034; /// R/W
    const uint32_t PreTrigger                  = 0x1038; /// R/W
    const uint32_t TriggerThreshold            = 0x106C; /// R/W
    const uint32_t TriggerHoldOffWidth         = 0x1074; /// R/W
    const uint32_t DPPAlgorithmControl         = 0x1080; /// R/W 
    const uint32_t ChannelStatus_R             = 0x1088; /// R
    const uint32_t AMCFirmwareRevision_R       = 0x108C; /// R
    const uint32_t ChannelDCOffset             = 0x1098; /// R/W
    const uint32_t ChannelADCTemperature_R     = 0x10A8; /// R
    const uint32_t IndividualSoftwareTrigger_W = 0x10C0; ///   W
    const uint32_t VetoWidth                   = 0x10D4; /// R/W
    
    /// I know there are many duplication, it is the design.
    const uint32_t BoardConfiguration          = 0x8000;  /// R/W
    const uint32_t AggregateOrganization       = 0x800C;  /// R/W
    const uint32_t ADCCalibration_W            = 0x809C;  ///   W
    const uint32_t ChannelShutdown_W           = 0x80BC;  ///   W
    const uint32_t AcquisitionControl          = 0x8100;  /// R/W
    const uint32_t AcquisitionStatus_R         = 0x8104;  /// R
    const uint32_t SoftwareTrigger_W           = 0x8108;  ///   W
    const uint32_t GlobalTriggerMask           = 0x810C;  /// R/W
    const uint32_t FrontPanelTRGOUTEnableMask  = 0x8110;  /// R/W
    const uint32_t LVDSIOData                  = 0x8118;  /// R/W
    const uint32_t FrontPanelIOControl         = 0x811C;  /// R/W
    const uint32_t ChannelEnableMask           = 0x8120;  /// R/W
    const uint32_t ROCFPGAFirmwareRevision_R   = 0x8124;  /// R
    const uint32_t EventStored_R               = 0x812C;  /// R
    const uint32_t VoltageLevelModeConfig      = 0x8138;  /// R/W
    const uint32_t SoftwareClockSync_W         = 0x813C;  ///   W
    const uint32_t BoardInfo_R                 = 0x8140;  /// R    /// [0:7] 0x0E = 725, 0x0B = 730, [8:15] 0x01 = 640 kSample, 0x08 = 5.12 MSample, [16:23] channel number
    const uint32_t AnalogMonitorMode           = 0x8144;  /// R/W
    const uint32_t EventSize_R                 = 0x814C;  /// R
    const uint32_t TimeBombDowncounter_R       = 0x8158;  /// R
    const uint32_t FanSpeedControl             = 0x8168;  /// R/W
    const uint32_t RunStartStopDelay           = 0x8170;  /// R/W
    const uint32_t BoardFailureStatus_R        = 0x8178;  /// R
    const uint32_t DisableExternalTrigger      = 0x817C;  /// R/W
    const uint32_t TriggerValidationMask_G     = 0x8180;  /// R/W,  0x8180 + 4n
    const uint32_t FrontPanelLVDSIONewFeatures = 0x81A0;  /// R/W
    const uint32_t BufferOccupancyGain         = 0x81B4;  /// R/W
    const uint32_t ExtendedVetoDelay           = 0x81C4;  /// R/W
    const uint32_t ReadoutControl              = 0xEF00;  /// R/W
    const uint32_t ReadoutStatus_R             = 0xEF04;  /// R
    const uint32_t BoardID                     = 0xEF08;  /// R/W  /// Geo address on VME crate
    const uint32_t MCSTBaseAddressAndControl   = 0xEF0C;  /// R/W
    const uint32_t RelocationAddress           = 0xEF10;  /// R/W
    const uint32_t InterruptStatusID           = 0xEF14;  /// R/W
    const uint32_t InterruptEventNumber        = 0xEF18;  /// R/W
    const uint32_t MaxAggregatePerBlockTransfer     = 0xEF1C;  /// R/W
    const uint32_t Scratch                     = 0xEF20;  /// R/W
    const uint32_t SoftwareReset_W             = 0xEF24;  ///   W
    const uint32_t SoftwareClear_W             = 0xEF28;  ///   W  
    const uint32_t ConfigurationReload_W       = 0xEF34;  ///   W
    const uint32_t ROMChecksum_R               = 0xF000;  /// R
    const uint32_t ROMChecksumByte2_R          = 0xF004;  /// R
    const uint32_t ROMChecksumByte1_R          = 0xF008;  /// R
    const uint32_t ROMChecksumByte0_R          = 0xF00C;  /// R
    const uint32_t ROMConstantByte2_R          = 0xF010;  /// R
    const uint32_t ROMConstantByte1_R          = 0xF014;  /// R
    const uint32_t ROMConstantByte0_R          = 0xF018;  /// R
    const uint32_t ROM_C_Code_R                = 0xF01C;  /// R
    const uint32_t ROM_R_Code_R                = 0xF020;  /// R
    const uint32_t ROM_IEEE_OUI_Byte2_R        = 0xF024;  /// R
    const uint32_t ROM_IEEE_OUI_Byte1_R        = 0xF028;  /// R
    const uint32_t ROM_IEEE_OUI_Byte0_R        = 0xF02C;  /// R
    const uint32_t ROM_BoardVersion_R          = 0xF030;  /// R
    const uint32_t ROM_BoardFromFactor_R       = 0xF034;  /// R
    const uint32_t ROM_BoardIDByte1_R          = 0xF038;  /// R
    const uint32_t ROM_BoardIDByte0_R          = 0xF03C;  /// R
    const uint32_t ROM_PCB_rev_Byte3_R         = 0xF040;  /// R
    const uint32_t ROM_PCB_rev_Byte2_R         = 0xF044;  /// R
    const uint32_t ROM_PCB_rev_Byte1_R         = 0xF048;  /// R
    const uint32_t ROM_PCB_rev_Byte0_R         = 0xF04C;  /// R
    const uint32_t ROM_FlashType_R             = 0xF050;  /// R
    const uint32_t ROM_BoardSerialNumByte1_R   = 0xF080;  /// R
    const uint32_t ROM_BoardSerialNumByte0_R   = 0xF084;  /// R
    const uint32_t ROM_VCXO_Type_R             = 0xF088;  /// R

    namespace PHA {
      const uint32_t DataFlush_W               = 0x103C; ///   W   not sure
      const uint32_t ChannelStopAcquisition    = 0x1040; /// R/W   not sure
      const uint32_t RCCR2SmoothingFactor      = 0x1054; /// R/W   Trigger Filter smoothing, triggerSmoothingFactor
      const uint32_t InputRiseTime             = 0x1058; /// R/W   OK
      const uint32_t TrapezoidRiseTime         = 0x105C; /// R/W   OK
      const uint32_t TrapezoidFlatTop          = 0x1060; /// R/W   OK
      const uint32_t PeakingTime               = 0x1064; /// R/W   OK
      const uint32_t DecayTime                 = 0x1068; /// R/W   OK
      const uint32_t TriggerThreshold          = 0x106C; /// R/W   OK
      const uint32_t RiseTimeValidationWindow  = 0x1070; /// R/W   OK
      const uint32_t TriggerHoldOffWidth       = 0x1074; /// R/W   OK
      const uint32_t PeakHoldOff               = 0x1078; /// R/W   OK
      const uint32_t ShapedTriggerWidth        = 0x1084; /// R/W   not sure
      const uint32_t DPPAlgorithmControl2_G    = 0x10A0; /// R/W   OK
      const uint32_t FineGain                  = 0x10C4; /// R/W   OK
    }

    namespace PSD  {
      const uint32_t CFDSetting                      = 0x103C; /// R/W
      const uint32_t ForcedDataFlush_W               = 0x1040; ///   W
      const uint32_t ChargeZeroSuppressionThreshold  = 0x1044; /// R/W
      const uint32_t ShortGateWidth                  = 0x1054; /// R/W
      const uint32_t LongGateWidth                   = 0x1058; /// R/W
      const uint32_t GateOffset                      = 0x105C; /// R/W
      const uint32_t TriggerThreshold                = 0x1060; /// R/W
      const uint32_t FixedBaseline                   = 0x1064; /// R/W
      const uint32_t TriggerLatency                  = 0x106C; /// R/W
      const uint32_t ShapedTriggerWidth              = 0x1070; /// R/W
      const uint32_t TriggerHoldOffWidth             = 0x1074; /// R/W
      const uint32_t ThresholdForPSDCut              = 0x1078; /// R/W
      const uint32_t PurGapThreshold                 = 0x107C; /// R/W
      const uint32_t DPPAlgorithmControl2_G          = 0x1084; /// R/W 
      const uint32_t EarlyBaselineFreeze             = 0x10D8; /// R/W
    }
  }
  
}
 

/**
/// This provides an alternative way for control
namespace Setting{
  
  enum PHA{
    /// board configuration
    AutoDataFlush_board_bool,
    DecimateWaveForm_board_bool,
    TriggerPropapation_board_bool,
    DualTrace_board_bool,
    AnalogProbe1_board_2bit,
    AnalogProbe2_board_2bit,
    WavefromRecording_board_bool,
    EnableExtra2Word_board_bool,
    EnergyRecording_board_bool,
    VirtualProbe_board_4bit,

    /// DPP Algorithm Control 1
    TrapazoidRescaling_5bit,
    WaveformDecimation_2bit,
    WaveformDecimationGain_2bit,
    PeakSampling_2bit,
    PulsePolarity_bool,
    TriggerMode_2bit,
    BaselineSampling_3bit,
    DisableSelfTrigger_bool,
    RolloverFlag_bool,
    PileupFlag_bool,

    /// DPP Algorithm Control 2
    LocalShapedTrigger_bool,
    LocalShapedTriggerMode_2bit,
    LocalTriggerValidation_bool,
    LocalTriggerValidationMode_2bit,
    Extra2WordOption_3bit,
    VetoSource_2bit,
    TriggerCounterRateStep_2bit,
    BaselineCalculationWhenACQOFF_bool,
    TagCorrelatedEvents_bool, 
    BaselineRestoreOptimization_bool,
    
    /// ACQ control 
    StartStopMode_2bit,
    StartStopACQ_bool,
    PLLClockSource_bool,
    VetoInForTRGOUT_bool,

    /// Global Trigger Mask
    GlobalTrgMask_8bit,
    GlobalTrgMajorityCoincienceWindow_4bit,
    GlobalTrgMajorityLevel_3bit,
    GlobalTrgExternalTrigger_bool,
    GlobalTrgSoftwareTrigger_bool,
    
    /// Front Panel TRG-OUT Mask
    FrontTRGOUTMask_8bit,
    FrontTRGOUTLogic_2bit,
    FrontTRGOUTMajorityLevel_3bit,
    FrontTRGOUTExternalTrigger_bool,
    FrontTRGOUTSoftwareTrigger_bool,
    
    /// Front Plane I/O 
    FrontPanelIO_LEMO_bool,
    FrontPanelIO_TRGOUT_bool,
    FrontPanelIO_TRGINCtrl_bool,
    FrontPanelIO_TRGINtoMezzanines_bool,
    FrontPanelIO_TRGOUTmode_6bit,
    
    /// Trigger Validation Mask
    TriggerValidationMask_8bit,
    TriggerValidationOperation_2bit,
    TriggerValidationMajority_3bit,
    TriggerValidationExternalTrigger_bool,
    TriggerValidationSoftwareTrigger_bool,
    
    /// Readout Control
    ReadoutCtrl_VMEInterruptLevel_3bit,
    ReadoutCtrl_OpticalLinkInterrupt_bool, 
    ReadoutCtrl_VMEBusError_bool,
    ReadoutCtrl_VMEAlign64_bool,
  
    /// Registers for channel
    RecordLength_G_ns,
    PreTriggerLength_ns,
    InputDynamicRange_bool,
    DCOffset_precentage,
    VetoWidth_ns,
    EventPreAggregate_G_max1023,
    AggregateOrganization_board_3bit,
    MaxAggregatePerBlockTransfer_board_10bit,
    
    TriggerThreshold_LSD,
    TriggerHoldOffWidth_ns,
    TriggerSmoothingFactor_5bit, /// RC-CR2 Smoothing Factor
    TriggerOutputWidth_ns,       /// Shaped Trigger Width
    InputRiseTime_ns,
    
    TrapezoidRiseTime_ns,
    TrapezoidFlatTop_ns,
    DecayTime_ns,
    PeakingTime_ns,
    PeakingHoldOff_ns,
    EnergyFineGain_16bit,
    RiseTimeValidationWindow_ns,
    
    ADCTemperature_8bit,
    
    /// Others
    FanSpeedControl_bool, 
    RunStartStopDelay_8bit,
    DisableExternalTrigger_bool,
    ExtendedVetoDelay_16bit,
    AnalogMonitorMode_3bit,
    BufferOccupancyGain_4bit,
    
    ///==========read only
    
    /// AMC Firmware Revisiion
    AMCFirmwareNumber_readOnly_8bit,
    AMCDPPcode_readOnly_8bit,
    AMCBuildDay_readOnly_8bit,
    AMCBuildMonth_readOnly_4bits,
    AMCBuildYear_readOnly_4bits,
    
    /// ACQ Status
    ACQStatus_readOnly_bool, 
    ACQEventReady_readOnly_bool,
    ACQEventFull_readOnly_bool, 
    ACQClockSource_readOnly_bool, 
    ACQPLLLock_readOnly_bool, 
    ACQBoardReady_readOnly_bool,
    ACQ_S_IN_Statue_readOnly_bool,
    ACQ_TRGIN_Status_readOnly_bool,
    ACQChannelShutDownStatus_readOnly_bool,
    ACQTenmperatureStatus_readOnly_4bit,
    
    
    ///========== not impletementd
    DataFlush_writeOnly_any,    /// any bit write, write only
    ChannelStopAcq_bool,
    ChannelSoftwareTrigger_writeOnly_any, 
    
    FineGain_16bit, /// this is complicated value
    
    ADCCalibration_32bit,
    
    ChannelsShutdown_bool,
    
    SoftwareTrigger_writeOnly_any, 
    
    ChannelEnableMask_16bit,
    
    /// ChannelStatus
    ChannelStatus_SPI_bool,
    ChannelStatus_ADCCalib_bool,
    ChannelStatus_ADCPowerDown_bool
    
  };
  
}*/

#endif