2023-04-11 11:13:23 -04:00
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#ifndef REGISTERADDRESS_H
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#define REGISTERADDRESS_H
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#include <vector>
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#include <string>
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#include <utility>
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2023-04-11 11:13:23 -04:00
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///=======
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/// All 0x1XXX registers are either indiviual or Group
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/// Indiviual register are all independence
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/// Group register, 2m and 2m+1 channels setting are shared. and the name will have _G as prefix
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/// Most 0x8XXX registers are common, which share for all channel
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/// For adding Register, two things needed.
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/// 1) add to the namepace
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/// 2) add to the RegisterXXXList
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/// The Reg Class has conversion operator
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/// Reg haha("haha", 0x1234);
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/// uint32_t papa = haha; /// papa = 0x1234
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2023-04-19 13:41:43 -04:00
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namespace Register {
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enum RW { ReadWrite, ReadONLY, WriteONLY};
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class Reg{
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public:
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Reg(){
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name = "";
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address = 0;
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type = RW::ReadWrite;
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group = 0;
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maxBit = 0;
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partialStep = 0;
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comboList.clear();
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}
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Reg(std::string name, uint32_t address, RW type = RW::ReadWrite, bool group = false, unsigned int max = 0, int pStep = 0){
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this->name = name;
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this->address = address;
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this->type = type;
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this->group = group;
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this->maxBit = max;
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this->partialStep = pStep;
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comboList.clear();
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};
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Reg(std::string name, uint32_t address, RW type = RW::ReadWrite, bool group = false, std::vector<std::pair<std::string, unsigned int>> list = {}){
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this->name = name;
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this->address = address;
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this->type = type;
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this->group = group;
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this->maxBit = 0;
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this->partialStep = 0;
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this->comboList = list;
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}
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~Reg(){};
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operator uint32_t () const {return this->address;} /// this allows Reg kaka("kaka", 0x1234) uint32_t haha = kaka;
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std::string GetName() const {return name;}
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const char * GetNameChar() const {return name.c_str();}
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uint32_t GetAddress() const {return address; }
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RW GetType() const {return type;}
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bool GetGroup() const {return group;}
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unsigned int GetMaxBit() const {return maxBit;}
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int GetPartialStep() const {return partialStep;} /// step = partialStep * ch2ns, -1 : step = 1
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void Print() const ;
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std::vector<std::pair<std::string, unsigned int>> GetComboList() const {return comboList;}
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uint32_t ActualAddress(int ch = -1){
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if( address == 0x8180 ) return (ch < 0 ? address : (address + 4*(ch/2)));
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if( address < 0x8000 ) return (ch < 0 ? (address + 0x7000) : (address + (ch << 8)) );
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if( address >= 0x8000 ) return address;
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return 0;
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}
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unsigned short Index (unsigned short ch);
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uint32_t CalAddress(unsigned int index); /// output actual address, also write the registerAddress
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void SetName(std::string str) {this->name = str;}
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private:
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std::string name;
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uint32_t address; /// This is the table of register, the actual address should call ActualAddress();
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RW type; /// read/write = 0; read = 1; write = 2
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bool group;
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unsigned int maxBit ;
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int partialStep;
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std::vector<std::pair<std::string, unsigned int>> comboList;
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};
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inline void Reg::Print() const{
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printf(" Name: %s\n", name.c_str());
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printf(" Re.Address: 0x%04X\n", address);
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printf(" Type: %s\n", type == RW::ReadWrite ? "Read/Write" : (type == RW::ReadONLY ? "Read-Only" : "Write-Only") );
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printf(" Group: %s\n", group ? "True" : "False");
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printf(" Max Value : 0x%X = %d \n", maxBit, maxBit);
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}
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inline unsigned short Reg::Index (unsigned short ch){
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unsigned short index;
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if( address == 0x8180){
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index = ((address + 4*(ch/2)) & 0x0FFF) / 4;
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}else if( address < 0x8000){
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index = (address + (ch << 8)) / 4;
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}else{
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if(address < 0xF000) {
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index = (address & 0x0FFF) / 4;
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}else{
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index = ((address & 0x0FFF) + 0x0200 ) / 4;
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}
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}
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return index;
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}
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inline uint32_t Reg::CalAddress(unsigned int index){
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uint32_t actualAddress = 0xFFFF;
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this->address = 0xFFFF;
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if( index < 0x0200 /4 ) {actualAddress = index * 4 + 0x8000; this->address = index * 4 + 0x8000; }
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if( 0x0200 / 4 <= index && index < 0x0300 /4 ) {actualAddress = index * 4 + 0xEE00; this->address = index * 4 + 0xEE00; }/// EE00 == F000 - 0200
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if( 0x0F00 / 4 <= index && index < 0x1000 /4 ) {actualAddress = index * 4 + 0xE000; this->address = index * 4 + 0xE000; }
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if( 0x1000 / 4 <= index ) {actualAddress = index * 4; this->address = (index * 4) & 0xF0FF; }
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///for TriggerValidationMask
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if( index == ((0x8180 + 4) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 4; address = 0x8180;} /// 1
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if( index == ((0x8180 + 8) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 8; address = 0x8180;} /// 2
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if( index == ((0x8180 + 12) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 12; address = 0x8180;} /// 3
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if( index == ((0x8180 + 16) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 16; address = 0x8180;} /// 4
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if( index == ((0x8180 + 20) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 20; address = 0x8180;} /// 5
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if( index == ((0x8180 + 24) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 24; address = 0x8180;} /// 6
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if( index == ((0x8180 + 28) & 0x0FFF) / 4 ) {actualAddress = 0x8180 + 28; address = 0x8180;} /// 7
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return actualAddress;
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}
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const Reg EventReadOutBuffer("EventReadOutBuffer", 0x0000, RW::ReadONLY, false, {}); /// R
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///========== Channel or Group
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const Reg ChannelDummy32 ("ChannelDummy32" , 0x1024, RW::ReadWrite, false, {}); /// R/W
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const Reg InputDynamicRange ("InputDynamicRange" , 0x1028, RW::ReadWrite, false, {}); /// R/W
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const Reg ChannelPulseWidth ("ChannelPulseWidth" , 0x1070, RW::ReadWrite, false, {}); /// R/W
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const Reg ChannelTriggerThreshold ("ChannelTriggerThreshold" , 0x1080, RW::ReadWrite, false, {}); /// R/W
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const Reg CoupleSelfTriggerLogic_G ("CoupleSelfTriggerLogic_G" , 0x1084, RW::ReadWrite, true, {}); /// R/W
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const Reg ChannelStatus_R ("ChannelStatus_R" , 0x1088, RW::ReadONLY, false, {}); /// R
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const Reg AMCFirmwareRevision_R ("AMCFirmwareRevision_R" , 0x108C, RW::ReadONLY, false, {}); /// R
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const Reg ChannelDCOffset ("ChannelDCOffset" , 0x1098, RW::ReadWrite, false, {}); /// R/W
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const Reg ChannelADCTemperature_R ("ChannelADCTemperature_R" , 0x10A8, RW::ReadONLY, false, {}); /// R
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const Reg ChannelSelfTriggerRateMeter_R ("ChannelSelfTriggerRateMeter_R", 0x10EC, RW::ReadONLY, false, {}); /// R
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///========== Board
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const Reg BoardConfiguration ("BoardConfiguration" , 0x8000, RW::ReadWrite, false, {}); /// R/W
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const Reg BufferOrganization ("BufferOrganization" , 0x800C, RW::ReadWrite, false, {}); /// R/W
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const Reg CustomSize ("CustomSize" , 0x8020, RW::ReadWrite, false, {}); /// R/W
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const Reg ADCCalibration_W ("ADCCalibration_W" , 0x809C, RW::WriteONLY, false, {}); /// W
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const Reg AcquisitionControl ("AcquisitionControl" , 0x8100, RW::ReadWrite, false, {}); /// R/W
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const Reg AcquisitionStatus_R ("AcquisitionStatus_R" , 0x8104, RW::ReadONLY , false, {}); /// R
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const Reg SoftwareTrigger_W ("SoftwareTrigger_W" , 0x8108, RW::WriteONLY, false, {}); /// W
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const Reg GlobalTriggerMask ("GlobalTriggerMask" , 0x810C, RW::ReadWrite, false, {}); /// R/W
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const Reg FrontPanelTRGOUTEnableMask ("FrontPanelTRGOUTEnableMask" , 0x8110, RW::ReadWrite, false, {}); /// R/W
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const Reg PostTrigger ("PostTrigger" , 0x8114, RW::ReadWrite, false, {}); /// R/W
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const Reg LVDSIOData ("LVDSIOData" , 0x8118, RW::ReadWrite, false, {}); /// R/W
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const Reg FrontPanelIOControl ("FrontPanelIOControl" , 0x811C, RW::ReadWrite, false, {}); /// R/W
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const Reg ChannelEnableMask ("ChannelEnableMask" , 0x8120, RW::ReadWrite, false, {}); /// R/W
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const Reg ROCFPGAFirmwareRevision_R ("ROCFPGAFirmwareRevision_R" , 0x8124, RW::ReadONLY , false, {}); /// R
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const Reg EventStored_R ("EventStored_R" , 0x812C, RW::ReadONLY , false, {}); /// R
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const Reg VoltageLevelModeConfig ("VoltageLevelModeConfig" , 0x8138, RW::ReadWrite, false, {}); /// R/W
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const Reg SoftwareClockSync_W ("SoftwareClockSync_W" , 0x813C, RW::WriteONLY, false, {}); /// W
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const Reg BoardInfo_R ("BoardInfo_R" , 0x8140, RW::ReadONLY , false, {}); /// R
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const Reg AnalogMonitorMode ("AnalogMonitorMode" , 0x8144, RW::ReadWrite, false, {}); /// R/W
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const Reg EventSize_R ("EventSize_R" , 0x814C, RW::ReadONLY , false, {}); /// R
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const Reg FanSpeedControl ("FanSpeedControl" , 0x8168, RW::ReadWrite, false, {}); /// R/W
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const Reg MemoryBufferAlmostFullLevel ("MemoryBufferAlmostFullLevel" , 0x816C, RW::ReadWrite, false, {}); /// R/W
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const Reg RunStartStopDelay ("RunStartStopDelay" , 0x8170, RW::ReadWrite, false, {}); /// R/W
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const Reg BoardFailureStatus_R ("BoardFailureStatus_R" , 0x8178, RW::ReadONLY , false, {}); /// R
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const Reg FrontPanelLVDSIONewFeatures ("FrontPanelLVDSIONewFeatures" , 0x81A0, RW::ReadWrite, false, {}); /// R/W
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const Reg BufferOccupancyGain ("BufferOccupancyGain" , 0x81B4, RW::ReadWrite, false, {}); /// R/W
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const Reg ChannelsShutdown_W ("ChannelsShutdown_W" , 0x81C0, RW::WriteONLY, false, {}); /// W
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const Reg ExtendedVetoDelay ("ExtendedVetoDelay" , 0x81C4, RW::ReadWrite, false, {}); /// R/W
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const Reg ReadoutControl ("ReadoutControl" , 0xEF00, RW::ReadWrite, false, {}); /// R/W
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const Reg ReadoutStatus_R ("ReadoutStatus_R" , 0xEF04, RW::ReadONLY , false, {}); /// R
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const Reg BoardID ("BoardID" , 0xEF08, RW::ReadWrite, false, {}); /// R/W
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const Reg MCSTBaseAddressAndControl ("MCSTBaseAddressAndControl" , 0xEF0C, RW::ReadWrite, false, {}); /// R/W
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const Reg RelocationAddress ("RelocationAddress" , 0xEF10, RW::ReadWrite, false, {}); /// R/W
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const Reg InterruptStatusID ("InterruptStatusID" , 0xEF14, RW::ReadWrite, false, {}); /// R/W
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const Reg InterruptEventNumber ("InterruptEventNumber" , 0xEF18, RW::ReadWrite, false, {}); /// R/W
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const Reg MaxAggregatePerBlockTransfer ("MaxAggregatePerBlockTransfer" , 0xEF1C, RW::ReadWrite, false, {}); /// R/W
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const Reg Scratch ("Scratch" , 0xEF20, RW::ReadWrite, false, {}); /// R/W
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const Reg SoftwareReset_W ("SoftwareReset_W" , 0xEF24, RW::WriteONLY, false, {}); /// W
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const Reg SoftwareClear_W ("SoftwareClear_W" , 0xEF28, RW::WriteONLY, false, {}); /// W
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///====== Common for PHA and PSD
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namespace DPP {
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namespace Bit_BoardConfig{
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const std::pair<unsigned short, unsigned short> EnableAutoDataFlush = {1, 0} ; /// length, smallest pos
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const std::pair<unsigned short, unsigned short> DecimateTrace = {1, 1} ;
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const std::pair<unsigned short, unsigned short> TrigPropagation = {1, 2} ;
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const std::pair<unsigned short, unsigned short> DualTrace = {1, 11} ;
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const std::pair<unsigned short, unsigned short> AnalogProbe1 = {2, 12} ;
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const std::pair<unsigned short, unsigned short> AnalogProbe2 = {2, 14} ;
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const std::pair<unsigned short, unsigned short> RecordTrace = {1, 16} ;
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const std::pair<unsigned short, unsigned short> EnableExtra2 = {1, 17} ;
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const std::pair<unsigned short, unsigned short> DigiProbel1 = {4, 20} ;
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const std::pair<unsigned short, unsigned short> DigiProbel2 = {3, 26} ;
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const std::vector<std::pair<std::string, unsigned int>> ListAnaProbe1 = {{"Input", 0},
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{"RC-CR", 1},
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{"RC-CR2", 2},
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{"Trapezoid", 3}};
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const std::vector<std::pair<std::string, unsigned int>> ListAnaProbe2 = {{"Input", 0},
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{"Threshold", 1},
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{"Trap. - Baseline", 2},
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{"Trap. Baseline", 3}};
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const std::vector<std::pair<std::string, unsigned int>> ListDigiProbe1 = {{"Peaking", 0},
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{"Armed", 1},
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{"Peak Run", 2},
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{"Pile Up", 3},
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{"peaking", 4},
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{"TRG Valid. Win", 5},
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{"Baseline Freeze", 6},
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{"TRG Holdoff", 7},
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{"TRG Valid.", 8},
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{"ACQ Busy", 9},
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{"Zero Cross", 10},
|
|
|
|
|
{"Ext. TRG", 11},
|
|
|
|
|
{"Budy", 12}};
|
|
|
|
|
|
2023-04-24 15:27:05 -04:00
|
|
|
}
|
2023-04-11 11:13:23 -04:00
|
|
|
|
2023-04-25 17:04:46 -04:00
|
|
|
namespace Bit_DPPAlgorithmControl {
|
2023-04-24 15:27:05 -04:00
|
|
|
const std::pair<unsigned short, unsigned short> TrapRescaling = {6, 0} ; /// length, smallest pos
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TraceDecimation = {2, 8};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TraceDeciGain = {2, 10,};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> PeakMean = {2, 12};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> Polarity = {1, 16};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TriggerMode = {2, 18};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> BaselineAvg = {3, 20};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> DisableSelfTrigger = {1, 24};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EnableRollOverFlag = {1, 26};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EnablePileUpFlag = {1, 27};
|
2023-04-26 16:39:54 -04:00
|
|
|
|
2023-04-24 15:27:05 -04:00
|
|
|
}
|
|
|
|
|
|
2023-04-25 17:04:46 -04:00
|
|
|
namespace Bit_AcquistionControl {
|
|
|
|
|
const std::pair<unsigned short, unsigned short> StartStopMode = {2, 0} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> ACQStartArm = {1, 2} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> PLLRef = {1, 6} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSBusyEnable = {1, 8} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSVetoEnable = {1, 9} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> VetoTRGOut = {1, 12} ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
namespace Bit_AcqStatus {
|
|
|
|
|
const std::pair<unsigned short, unsigned short> AcqStatus = {1, 2} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EventReady = {1, 3} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EventFull = {1, 4} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> ClockSource = {1, 5} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> PLLLock = {1, 7} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> BoardReady = {1, 8} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> SINStatus = {1, 15} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TRGINStatus = {1, 16} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> ChannelsDown = {1, 19} ;
|
|
|
|
|
}
|
|
|
|
|
|
2023-04-26 16:39:54 -04:00
|
|
|
namespace Bit_ReadoutControl {
|
|
|
|
|
const std::pair<unsigned short, unsigned short> VMEInterruptLevel = {3, 0} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EnableOpticalLinkInpt = {1, 3} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EnableEventAligned = {1, 4} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> VMEAlign64Mode = {1, 5} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> VMEBaseAddressReclocated = {1, 6} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> InterrupReleaseMode = {1, 7} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> EnableExtendedBlockTransfer = {1, 8} ;
|
2023-04-28 18:18:12 -04:00
|
|
|
}
|
2023-04-26 16:39:54 -04:00
|
|
|
|
2023-04-28 18:18:12 -04:00
|
|
|
namespace Bit_FrontPanelIOControl {
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LEMOLevel = {1, 0} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> DisableTrgOut = {1, 1} ;
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSDirection1 = {1, 2} ; // [3:0]
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSDirection2 = {1, 3} ; // [7:4]
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSDirection3 = {1, 4} ; // [11:8]
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSDirection4 = {1, 5} ; // [15:12]
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSConfiguration = {2, 6};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSNewFeature = {1, 8};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> LVDSLatchMode = {1, 9};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TRGINMode = {1, 10};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TRGINMezzanine = {1, 11};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> TRGOUTConfig = {6, 14};
|
|
|
|
|
const std::pair<unsigned short, unsigned short> PatternConfig = {2, 21};
|
|
|
|
|
|
|
|
|
|
const std::vector<std::pair<std::string, unsigned int>> ListLEMOLevel = {{"NIM I/O", 0},
|
|
|
|
|
{"TTL I/O", 1}};
|
|
|
|
|
const std::vector<std::pair<std::string, unsigned int>> ListTRGIMode = {{"Edge of TRG-IN", 0},
|
|
|
|
|
{"Whole duration of TR-IN", 1}};
|
|
|
|
|
const std::vector<std::pair<std::string, unsigned int>> ListTRGIMezzanine = {{"Pocessed by Motherboard", 0},
|
|
|
|
|
{"Skip Motherboard", 1}};
|
|
|
|
|
|
|
|
|
|
const std::vector<std::pair<std::string, unsigned int>> ListTRGOUTConfig = {{"Disable", 0x00002}, /// this is TRG_OUT high imped. 0x811C bit[1]
|
|
|
|
|
{"force TRG-OUT is 0", 0x08000},
|
|
|
|
|
{"force TRG-OUT is 1", 0x0C000},
|
|
|
|
|
{"Trigger (Mask)", 0x00000},
|
|
|
|
|
{"Channel Probe", 0x20000},
|
|
|
|
|
{"S-IN", 0x30000},
|
|
|
|
|
{"RUN", 0x10000},
|
|
|
|
|
{"Sync Clock", 0x50000},
|
|
|
|
|
{"Clock Phase", 0x90000},
|
|
|
|
|
{"BUSY/UNLOCK", 0xD0000}};
|
2023-04-26 16:39:54 -04:00
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2023-04-21 18:10:12 -04:00
|
|
|
const Reg RecordLength_G ("RecordLength_G" , 0x1020, RW::ReadWrite, true, 0x3FFF, 8); /// R/W
|
|
|
|
|
const Reg InputDynamicRange ("InputDynamicRange" , 0x1028, RW::ReadWrite, false, {{"2 Vpp", 0},{"0.5 Vpp", 1}}); /// R/W
|
|
|
|
|
const Reg NumberEventsPerAggregate_G ("NumberEventsPerAggregate_G" , 0x1034, RW::ReadWrite, true, 0x3FF, -1); /// R/W
|
|
|
|
|
const Reg PreTrigger ("PreTrigger" , 0x1038, RW::ReadWrite, false, 0xFF, 4); /// R/W
|
|
|
|
|
const Reg TriggerThreshold ("TriggerThreshold" , 0x106C, RW::ReadWrite, false, 0x3FFF, -1); /// R/W
|
|
|
|
|
const Reg TriggerHoldOffWidth ("TriggerHoldOffWidth" , 0x1074, RW::ReadWrite, false, 0x3FF, 4); /// R/W
|
|
|
|
|
const Reg DPPAlgorithmControl ("DPPAlgorithmControl" , 0x1080, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg ChannelStatus_R ("ChannelStatus_R" , 0x1088, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg AMCFirmwareRevision_R ("AMCFirmwareRevision_R" , 0x108C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ChannelDCOffset ("ChannelDCOffset" , 0x1098, RW::ReadWrite, false, 0xFFFF, -1); /// R/W
|
|
|
|
|
const Reg ChannelADCTemperature_R ("ChannelADCTemperature_R" , 0x10A8, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg IndividualSoftwareTrigger_W ("IndividualSoftwareTrigger_W" , 0x10C0, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg VetoWidth ("VetoWidth" , 0x10D4, RW::ReadWrite, false, {}); /// R/W
|
2023-04-11 11:13:23 -04:00
|
|
|
|
|
|
|
|
/// I know there are many duplication, it is the design.
|
2023-04-21 18:10:12 -04:00
|
|
|
const Reg BoardConfiguration ("BoardConfiguration" , 0x8000, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg AggregateOrganization ("AggregateOrganization" , 0x800C, RW::ReadWrite, false, {{"Not use", 0x0},
|
|
|
|
|
{"Not use", 0x1},
|
|
|
|
|
{ "4", 0x2},
|
|
|
|
|
{ "8", 0x3},
|
|
|
|
|
{ "16", 0x4},
|
|
|
|
|
{ "32", 0x5},
|
|
|
|
|
{ "64", 0x6},
|
|
|
|
|
{ "128", 0x7},
|
|
|
|
|
{ "256", 0x8},
|
|
|
|
|
{ "512", 0x9},
|
|
|
|
|
{"1024", 0xA}}); /// R/W
|
|
|
|
|
const Reg ADCCalibration_W ("ADCCalibration_W" , 0x809C, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg ChannelShutdown_W ("ChannelShutdown_W" , 0x80BC, RW::WriteONLY, false, {{"no shutdown", 0},{"shutdown", 1}}); /// W
|
|
|
|
|
const Reg AcquisitionControl ("AcquisitionControl" , 0x8100, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg AcquisitionStatus_R ("AcquisitionStatus_R" , 0x8104, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg SoftwareTrigger_W ("SoftwareTrigger_W" , 0x8108, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg GlobalTriggerMask ("GlobalTriggerMask" , 0x810C, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg FrontPanelTRGOUTEnableMask ("FrontPanelTRGOUTEnableMask" , 0x8110, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg LVDSIOData ("LVDSIOData" , 0x8118, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg FrontPanelIOControl ("FrontPanelIOControl" , 0x811C, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg ChannelEnableMask ("ChannelEnableMask" , 0x8120, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg ROCFPGAFirmwareRevision_R ("ROCFPGAFirmwareRevision_R" , 0x8124, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg EventStored_R ("EventStored_R" , 0x812C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg VoltageLevelModeConfig ("VoltageLevelModeConfig" , 0x8138, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg SoftwareClockSync_W ("SoftwareClockSync_W" , 0x813C, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg BoardInfo_R ("BoardInfo_R" , 0x8140, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg AnalogMonitorMode ("AnalogMonitorMode" , 0x8144, RW::ReadWrite, false, {{"Trig. Maj. Mode", 0},
|
|
|
|
|
{"Test mode", 1},
|
|
|
|
|
{"Buffer occp. Mode", 3},
|
|
|
|
|
{"Voltage Lvl Mode", 4}}); /// R/W
|
|
|
|
|
const Reg EventSize_R ("EventSize_R" , 0x814C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg TimeBombDowncounter_R ("TimeBombDowncounter_R" , 0x8158, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg FanSpeedControl ("FanSpeedControl" , 0x8168, RW::ReadWrite, false, {}); /// R/W
|
2023-04-26 16:39:54 -04:00
|
|
|
const Reg RunStartStopDelay ("RunStartStopDelay" , 0x8170, RW::ReadWrite, false, 0xFF, 8); /// R/W
|
2023-04-21 18:10:12 -04:00
|
|
|
const Reg BoardFailureStatus_R ("BoardFailureStatus_R" , 0x8178, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg DisableExternalTrigger ("DisableExternalTrigger" , 0x817C, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg FrontPanelLVDSIONewFeatures ("FrontPanelLVDSIONewFeatures" , 0x81A0, RW::ReadWrite, false, {}); /// R/W
|
2023-04-26 16:39:54 -04:00
|
|
|
const Reg BufferOccupancyGain ("BufferOccupancyGain" , 0x81B4, RW::ReadWrite, false, 0xF, -1); /// R/W
|
|
|
|
|
const Reg ExtendedVetoDelay ("ExtendedVetoDelay" , 0x81C4, RW::ReadWrite, false, 0xFFFF, 4); /// R/W
|
2023-04-21 18:10:12 -04:00
|
|
|
const Reg ReadoutControl ("ReadoutControl" , 0xEF00, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg ReadoutStatus_R ("ReadoutStatus_R" , 0xEF04, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg BoardID ("BoardID" , 0xEF08, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg MCSTBaseAddressAndControl ("MCSTBaseAddressAndControl" , 0xEF0C, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg RelocationAddress ("RelocationAddress" , 0xEF10, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg InterruptStatusID ("InterruptStatusID" , 0xEF14, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg InterruptEventNumber ("InterruptEventNumber" , 0xEF18, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg MaxAggregatePerBlockTransfer("MaxAggregatePerBlockTransfer", 0xEF1C, RW::ReadWrite, false, 0x3FF, -1); /// R/W
|
|
|
|
|
const Reg Scratch ("Scratch" , 0xEF20, RW::ReadWrite, false, {}); /// R/W
|
|
|
|
|
const Reg SoftwareReset_W ("SoftwareReset_W" , 0xEF24, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg SoftwareClear_W ("SoftwareClear_W" , 0xEF28, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg ConfigurationReload_W ("ConfigurationReload_W" , 0xEF34, RW::WriteONLY, false, {}); /// W
|
|
|
|
|
const Reg ROMChecksum_R ("ROMChecksum_R" , 0xF000, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROMChecksumByte2_R ("ROMChecksumByte2_R" , 0xF004, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROMChecksumByte1_R ("ROMChecksumByte1_R" , 0xF008, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROMChecksumByte0_R ("ROMChecksumByte0_R" , 0xF00C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROMConstantByte2_R ("ROMConstantByte2_R" , 0xF010, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROMConstantByte1_R ("ROMConstantByte1_R" , 0xF014, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROMConstantByte0_R ("ROMConstantByte0_R" , 0xF018, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_C_Code_R ("ROM_C_Code_R" , 0xF01C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_R_Code_R ("ROM_R_Code_R" , 0xF020, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_IEEE_OUI_Byte2_R ("ROM_IEEE_OUI_Byte2_R" , 0xF024, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_IEEE_OUI_Byte1_R ("ROM_IEEE_OUI_Byte1_R" , 0xF028, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_IEEE_OUI_Byte0_R ("ROM_IEEE_OUI_Byte0_R" , 0xF02C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_BoardVersion_R ("ROM_BoardVersion_R" , 0xF030, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_BoardFromFactor_R ("ROM_BoardFromFactor_R" , 0xF034, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_BoardIDByte1_R ("ROM_BoardIDByte1_R" , 0xF038, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_BoardIDByte0_R ("ROM_BoardIDByte0_R" , 0xF03C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_PCB_rev_Byte3_R ("ROM_PCB_rev_Byte3_R" , 0xF040, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_PCB_rev_Byte2_R ("ROM_PCB_rev_Byte2_R" , 0xF044, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_PCB_rev_Byte1_R ("ROM_PCB_rev_Byte1_R" , 0xF048, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_PCB_rev_Byte0_R ("ROM_PCB_rev_Byte0_R" , 0xF04C, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_FlashType_R ("ROM_FlashType_R" , 0xF050, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_BoardSerialNumByte1_R ("ROM_BoardSerialNumByte1_R" , 0xF080, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_BoardSerialNumByte0_R ("ROM_BoardSerialNumByte0_R" , 0xF084, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
const Reg ROM_VCXO_Type_R ("ROM_VCXO_Type_R" , 0xF088, RW::ReadONLY , false, {}); /// R
|
|
|
|
|
|
|
|
|
|
const Reg TriggerValidationMask_G ("TriggerValidationMask_G" , 0x8180, RW::ReadWrite, true, {}); /// R/W,
|
2023-04-11 11:13:23 -04:00
|
|
|
|
|
|
|
|
namespace PHA {
|
2023-04-21 18:10:12 -04:00
|
|
|
const Reg DataFlush_W ("DataFlush_W" , 0x103C, RW::WriteONLY, false, {}); /// W not sure
|
|
|
|
|
const Reg ChannelStopAcquisition ("ChannelStopAcquisition" , 0x1040, RW::ReadWrite, false, {{"Run", 0}, {"Stop", 1}}); /// R/W not sure
|
|
|
|
|
const Reg RCCR2SmoothingFactor ("RCCR2SmoothingFactor" , 0x1054, RW::ReadWrite, false, {{ "Disabled", 0x0},
|
|
|
|
|
{ "2 sample", 0x1},
|
|
|
|
|
{ "4 sample", 0x2},
|
|
|
|
|
{ "8 sample", 0x4},
|
|
|
|
|
{ "16 sample", 0x8},
|
|
|
|
|
{ "32 sample", 0x10},
|
|
|
|
|
{ "64 sample", 0x20},
|
|
|
|
|
{"128 sample", 0x3F}
|
|
|
|
|
}); /// R/W Trigger Filter smoothing, triggerSmoothingFactor
|
|
|
|
|
const Reg InputRiseTime ("InputRiseTime" , 0x1058, RW::ReadWrite, false, 0xFF, 4); /// R/W OK
|
|
|
|
|
const Reg TrapezoidRiseTime ("TrapezoidRiseTime" , 0x105C, RW::ReadWrite, false, 0xFFF, 4); /// R/W OK
|
|
|
|
|
const Reg TrapezoidFlatTop ("TrapezoidFlatTop" , 0x1060, RW::ReadWrite, false, 0xFFF, 4); /// R/W OK
|
|
|
|
|
const Reg PeakingTime ("PeakingTime" , 0x1064, RW::ReadWrite, false, 0xFFF, 4); /// R/W OK
|
|
|
|
|
const Reg DecayTime ("DecayTime" , 0x1068, RW::ReadWrite, false, 0xFFFF, 4); /// R/W OK
|
|
|
|
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const Reg TriggerThreshold ("TriggerThreshold" , 0x106C, RW::ReadWrite, false, 0x3FFF, -1); /// R/W OK
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const Reg RiseTimeValidationWindow ("RiseTimeValidationWindow" , 0x1070, RW::ReadWrite, false, 0x3FF, 1); /// R/W OK
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const Reg TriggerHoldOffWidth ("TriggerHoldOffWidth" , 0x1074, RW::ReadWrite, false, 0x3FF, 4); /// R/W OK
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const Reg PeakHoldOff ("PeakHoldOff" , 0x1078, RW::ReadWrite, false, 0x3FF, 4); /// R/W OK
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const Reg ShapedTriggerWidth ("ShapedTriggerWidth" , 0x1084, RW::ReadWrite, false, 0x3FF, 4); /// R/W not sure
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const Reg DPPAlgorithmControl2_G ("DPPAlgorithmControl2_G" , 0x10A0, RW::ReadWrite, true, {}); /// R/W OK
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const Reg FineGain ("FineGain" , 0x10C4, RW::ReadWrite, false, {}); /// R/W OK
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2023-04-11 11:13:23 -04:00
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}
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namespace PSD {
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2023-04-21 18:10:12 -04:00
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const Reg CFDSetting ("CFDSetting" , 0x103C, RW::ReadWrite, false, {}); /// R/W
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const Reg ForcedDataFlush_W ("ForcedDataFlush_W" , 0x1040, RW::WriteONLY, false, {}); /// W
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const Reg ChargeZeroSuppressionThreshold ("ChargeZeroSuppressionThreshold" , 0x1044, RW::ReadWrite, false, {}); /// R/W
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const Reg ShortGateWidth ("ShortGateWidth" , 0x1054, RW::ReadWrite, false, {}); /// R/W
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const Reg LongGateWidth ("LongGateWidth" , 0x1058, RW::ReadWrite, false, {}); /// R/W
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const Reg GateOffset ("GateOffset" , 0x105C, RW::ReadWrite, false, {}); /// R/W
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const Reg TriggerThreshold ("TriggerThreshold" , 0x1060, RW::ReadWrite, false, {}); /// R/W
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const Reg FixedBaseline ("FixedBaseline" , 0x1064, RW::ReadWrite, false, {}); /// R/W
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const Reg TriggerLatency ("TriggerLatency" , 0x106C, RW::ReadWrite, false, {}); /// R/W
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const Reg ShapedTriggerWidth ("ShapedTriggerWidth" , 0x1070, RW::ReadWrite, false, {}); /// R/W
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const Reg TriggerHoldOffWidth ("TriggerHoldOffWidth" , 0x1074, RW::ReadWrite, false, {}); /// R/W
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const Reg ThresholdForPSDCut ("ThresholdForPSDCut" , 0x1078, RW::ReadWrite, false, {}); /// R/W
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const Reg PurGapThreshold ("PurGapThreshold" , 0x107C, RW::ReadWrite, false, {}); /// R/W
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const Reg DPPAlgorithmControl2_G ("DPPAlgorithmControl2_G" , 0x1084, RW::ReadWrite, true, {}); /// R/W
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const Reg EarlyBaselineFreeze ("EarlyBaselineFreeze" , 0x10D8, RW::ReadWrite, true, {}); /// R/W
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2023-04-11 11:13:23 -04:00
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}
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}
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2023-04-19 13:41:43 -04:00
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}; // end of namepace Register
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2023-04-11 11:13:23 -04:00
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2023-04-19 13:41:43 -04:00
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const std::vector<Register::Reg> RegisterPHAList = {
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2023-04-11 11:13:23 -04:00
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Register::DPP::PHA::DataFlush_W ,
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Register::DPP::PHA::ChannelStopAcquisition ,
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Register::DPP::PHA::RCCR2SmoothingFactor ,
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Register::DPP::PHA::InputRiseTime ,
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Register::DPP::PHA::TrapezoidRiseTime ,
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Register::DPP::PHA::TrapezoidFlatTop ,
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Register::DPP::PHA::PeakingTime ,
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Register::DPP::PHA::DecayTime ,
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Register::DPP::PHA::TriggerThreshold ,
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Register::DPP::PHA::RiseTimeValidationWindow ,
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Register::DPP::PHA::TriggerHoldOffWidth ,
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Register::DPP::PHA::PeakHoldOff ,
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Register::DPP::PHA::ShapedTriggerWidth ,
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Register::DPP::PHA::DPPAlgorithmControl2_G ,
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Register::DPP::PHA::FineGain ,
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Register::DPP::RecordLength_G ,
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Register::DPP::InputDynamicRange ,
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Register::DPP::NumberEventsPerAggregate_G ,
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Register::DPP::PreTrigger ,
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Register::DPP::TriggerThreshold ,
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Register::DPP::TriggerHoldOffWidth ,
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Register::DPP::DPPAlgorithmControl ,
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Register::DPP::ChannelStatus_R ,
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Register::DPP::AMCFirmwareRevision_R ,
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Register::DPP::ChannelDCOffset ,
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Register::DPP::ChannelADCTemperature_R ,
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Register::DPP::IndividualSoftwareTrigger_W,
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Register::DPP::VetoWidth ,
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Register::DPP::TriggerValidationMask_G
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};
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2023-04-19 13:41:43 -04:00
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const std::vector<Register::Reg> RegisterPSDList = {
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2023-04-11 11:13:23 -04:00
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Register::DPP::PSD::CFDSetting ,
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Register::DPP::PSD::ForcedDataFlush_W ,
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Register::DPP::PSD::ChargeZeroSuppressionThreshold ,
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Register::DPP::PSD::ShortGateWidth ,
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Register::DPP::PSD::LongGateWidth ,
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Register::DPP::PSD::GateOffset ,
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Register::DPP::PSD::TriggerThreshold ,
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Register::DPP::PSD::FixedBaseline ,
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Register::DPP::PSD::TriggerLatency ,
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Register::DPP::PSD::ShapedTriggerWidth ,
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Register::DPP::PSD::TriggerHoldOffWidth ,
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Register::DPP::PSD::ThresholdForPSDCut ,
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Register::DPP::PSD::PurGapThreshold ,
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Register::DPP::PSD::DPPAlgorithmControl2_G ,
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Register::DPP::PSD::EarlyBaselineFreeze ,
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Register::DPP::RecordLength_G ,
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Register::DPP::InputDynamicRange ,
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Register::DPP::NumberEventsPerAggregate_G ,
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Register::DPP::PreTrigger ,
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Register::DPP::TriggerThreshold ,
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Register::DPP::TriggerHoldOffWidth ,
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Register::DPP::DPPAlgorithmControl ,
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Register::DPP::ChannelStatus_R ,
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Register::DPP::AMCFirmwareRevision_R ,
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Register::DPP::ChannelDCOffset ,
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Register::DPP::ChannelADCTemperature_R ,
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Register::DPP::IndividualSoftwareTrigger_W,
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Register::DPP::VetoWidth ,
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Register::DPP::TriggerValidationMask_G
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};
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/// Only Board Setting
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2023-04-19 13:41:43 -04:00
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const std::vector<Register::Reg> RegisterDPPList = {
|
2023-04-11 11:13:23 -04:00
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Register::DPP::BoardConfiguration ,
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Register::DPP::AggregateOrganization ,
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Register::DPP::ADCCalibration_W ,
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Register::DPP::ChannelShutdown_W ,
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Register::DPP::AcquisitionControl ,
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Register::DPP::AcquisitionStatus_R ,
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Register::DPP::SoftwareTrigger_W ,
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Register::DPP::GlobalTriggerMask ,
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Register::DPP::FrontPanelTRGOUTEnableMask ,
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Register::DPP::LVDSIOData ,
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Register::DPP::FrontPanelIOControl ,
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Register::DPP::ChannelEnableMask ,
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Register::DPP::ROCFPGAFirmwareRevision_R ,
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Register::DPP::EventStored_R ,
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Register::DPP::VoltageLevelModeConfig ,
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Register::DPP::SoftwareClockSync_W ,
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Register::DPP::BoardInfo_R ,
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Register::DPP::AnalogMonitorMode ,
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Register::DPP::EventSize_R ,
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Register::DPP::TimeBombDowncounter_R ,
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Register::DPP::FanSpeedControl ,
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Register::DPP::RunStartStopDelay ,
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Register::DPP::BoardFailureStatus_R ,
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Register::DPP::DisableExternalTrigger ,
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Register::DPP::FrontPanelLVDSIONewFeatures ,
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Register::DPP::BufferOccupancyGain ,
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Register::DPP::ExtendedVetoDelay ,
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Register::DPP::ReadoutControl ,
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Register::DPP::ReadoutStatus_R ,
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Register::DPP::BoardID ,
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Register::DPP::MCSTBaseAddressAndControl ,
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Register::DPP::RelocationAddress ,
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Register::DPP::InterruptStatusID ,
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Register::DPP::InterruptEventNumber ,
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Register::DPP::MaxAggregatePerBlockTransfer,
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Register::DPP::Scratch ,
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Register::DPP::SoftwareReset_W ,
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Register::DPP::SoftwareClear_W ,
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Register::DPP::ConfigurationReload_W ,
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Register::DPP::ROMChecksum_R ,
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Register::DPP::ROMChecksumByte2_R ,
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Register::DPP::ROMChecksumByte1_R ,
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Register::DPP::ROMChecksumByte0_R ,
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Register::DPP::ROMConstantByte2_R ,
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Register::DPP::ROMConstantByte1_R ,
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Register::DPP::ROMConstantByte0_R ,
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Register::DPP::ROM_C_Code_R ,
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Register::DPP::ROM_R_Code_R ,
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Register::DPP::ROM_IEEE_OUI_Byte2_R ,
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Register::DPP::ROM_IEEE_OUI_Byte1_R ,
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Register::DPP::ROM_IEEE_OUI_Byte0_R ,
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Register::DPP::ROM_BoardVersion_R ,
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Register::DPP::ROM_BoardFromFactor_R ,
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Register::DPP::ROM_BoardIDByte1_R ,
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Register::DPP::ROM_BoardIDByte0_R ,
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Register::DPP::ROM_PCB_rev_Byte3_R ,
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Register::DPP::ROM_PCB_rev_Byte2_R ,
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Register::DPP::ROM_PCB_rev_Byte1_R ,
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Register::DPP::ROM_PCB_rev_Byte0_R ,
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Register::DPP::ROM_FlashType_R ,
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Register::DPP::ROM_BoardSerialNumByte1_R ,
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Register::DPP::ROM_BoardSerialNumByte0_R ,
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Register::DPP::ROM_VCXO_Type_R
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};
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#endif
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