rtang/FSUDAQ_Qt6
1
0
Fork 0
Code Issues Pull Requests 1 Projects Releases 3 Wiki Activity

edited README.md

Browse Source
This commit is contained in:
carina@hades 2023-10-20 17:05:40 -04:00
parent 7ed353ae08
commit 8a982a375f
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
README.md
View File

@ -105,10 +105,11 @@ Those file can be compiled using
# Known Issues
* DC offset issue. When porgram default settings, the DC offset is not the same for all channels.
* for PHA firmware, when the trigger average changed, the Events per Agg need to be changed.
* for PHA firmware, when the trigger rate changed, the Events per Agg need to be changed.
* The Agg Organization, Event per Agg, Record Length are strongly correlated. Some settings are invalid and will cause the digitizer goes crazy.
* Sometimes, the buffer is not in time order, and make the trigger/Accept rate to be nagative. This is nothing to do with the program but the digitizer settings. Recommand reporgram the digitizer.
* for 1740 QDC, RecordLenght is board setting, but readout is indivuial group.
# Known Bugs
* There is no known bug. Please report if you find one.