seperate out ProgramChannel from ProgramBoard in Digitizer Class
This commit is contained in:
parent
81b2fba623
commit
9bdd6b77eb
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@ -328,181 +328,173 @@ void Digitizer::ProgramBoard(){
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int Digitizer::ProgramBoard_PHA(){
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DebugPrint("%s", "Digitizer");
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printf("===== Digitizer::%s\n", __func__);
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//ret = CAEN_DGTZ_Reset(handle);
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Reset();
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::RecordLength_G + 0x7000, 62);
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//*========================== Board
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/// change address 0xEF08 (5 bits), this will reflected in the 2nd word of the Board Agg. header.
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardID, (DPPType & 0xF));
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//WriteRegister(DPP::BoardID, (DPPType & 0xF));
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//ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0F8915); /// has Extra2, dual trace, input and trap-baseline
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0E8915); /// has Extra2, no trace
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ret |= CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0E8915); /// has Extra2, no trace
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//ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0D8115); /// diable Extra2
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//TODO change to write register
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ret = CAEN_DGTZ_SetAcquisitionMode(handle, CAEN_DGTZ_SW_CONTROLLED); /// software command
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ret |= CAEN_DGTZ_SetChannelEnableMask(handle, ModelType == ModelTypeCode::VME ? 0xFFFF : 0x00FF);
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ret |= CAEN_DGTZ_SetRunSynchronizationMode(handle, CAEN_DGTZ_RUN_SYNC_Disabled);
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ret |= CAEN_DGTZ_SetIOLevel(handle, CAEN_DGTZ_IOLevel_NIM);
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ret |= CAEN_DGTZ_SetExtTriggerInputMode(handle, CAEN_DGTZ_TRGMODE_ACQ_ONLY);
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ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(DPP::GlobalTriggerMask), 0x0);
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ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(DPP::FrontPanelTRGOUTEnableMask), 0x0);
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ret = CAEN_DGTZ_SetChannelEnableMask(handle, ModelType == ModelTypeCode::VME ? 0xFFFF : 0x00FF);
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//ret = CAEN_DGTZ_SetNumEventsPerAggregate(handle, 0);
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ret = CAEN_DGTZ_SetRunSynchronizationMode(handle, CAEN_DGTZ_RUN_SYNC_Disabled);
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if( ret != 0 ) { printf("==== set board error.\n"); return 0;}
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uint32_t address;
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address = DPP::PHA::DecayTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 5000 );
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address = DPP::PHA::TrapezoidFlatTop; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x1A );
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address = DPP::PHA::TrapezoidRiseTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 6 );
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address = DPP::PHA::PeakingTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 6 );
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address = DPP::PHA::RCCR2SmoothingFactor; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 4 );
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address = DPP::PHA::InputRiseTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 6 );
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address = DPP::PHA::TriggerThreshold; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 1000 );
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address = DPP::PHA::PeakHoldOff; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x3E );
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address = DPP::PHA::TriggerHoldOffWidth; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x3E );
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address = DPP::PHA::RiseTimeValidationWindow;ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x0 );
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x0, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x1, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x2, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x3, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x4, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x5, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x6, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x7, 0xAAAA);
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if( ModelType == ModelTypeCode::VME ){
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x8, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x9, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xA, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xB, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xC, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xD, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xE, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xF, 0xAAAA);
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}
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PreTrigger) + 0x7000 , 32 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::InputDynamicRange) + 0x7000 , 0x0 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(DPP::DPPAlgorithmControl) + 0x7000, 0x030200f);
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if( ret != 0 ) { printf("!!!!!!!! set channels error.\n");}
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AutoSetDPPEventAggregation();
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/// change address 0xEF08 (5 bits), this will reflected in the 2nd word of the Board Agg. header.
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardID, (DPPType & 0xF));
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//WriteRegister(DPP::BoardID, (DPPType & 0xF));
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//*========================== Group
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ProgramChannel_PHA(-1);
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isSettingFilledinMemeory = false; /// unlock the ReadAllSettingsFromBoard();
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usleep(1000*300);
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ReadAllSettingsFromBoard();
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return ret;
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}
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int Digitizer::ProgramChannel_PHA(short ch){
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DebugPrint("%s", "Digitizer");
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printf("===== Digitizer::%s|ch:%d\n", __func__,ch);
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uint32_t channel = (ch << 8);
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if( ch < 0 ) channel = 0x7000;
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uint32_t address = (ch << 8);
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address = channel + DPP::RecordLength_G; ret = CAEN_DGTZ_WriteRegister(handle, address, 62);
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address = channel + DPP::PHA::DecayTime; ret |= CAEN_DGTZ_WriteRegister(handle, address, 5000 );
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address = channel + DPP::PHA::TrapezoidFlatTop; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x1A );
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address = channel + DPP::PHA::TrapezoidRiseTime; ret |= CAEN_DGTZ_WriteRegister(handle, address, 6 );
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address = channel + DPP::PHA::PeakingTime; ret |= CAEN_DGTZ_WriteRegister(handle, address, 6 );
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address = channel + DPP::PHA::RCCR2SmoothingFactor; ret |= CAEN_DGTZ_WriteRegister(handle, address, 4 );
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address = channel + DPP::PHA::InputRiseTime; ret |= CAEN_DGTZ_WriteRegister(handle, address, 6 );
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address = channel + DPP::PHA::TriggerThreshold; ret |= CAEN_DGTZ_WriteRegister(handle, address, 1000 );
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address = channel + DPP::PHA::PeakHoldOff; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x3E );
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address = channel + DPP::PHA::TriggerHoldOffWidth; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x3E );
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address = channel + DPP::PHA::RiseTimeValidationWindow;ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x0 );
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address = channel + DPP::PreTrigger; ret |= CAEN_DGTZ_WriteRegister(handle, address, 32 );
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address = channel + DPP::InputDynamicRange; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x0 );
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address = channel + DPP::DPPAlgorithmControl; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x030200f);
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address = channel + DPP::PHA::DPPAlgorithmControl2_G; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x200); // use fine time
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if( ch >= 0 ) {
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, ch, 0xAAAA);
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}else{
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for( int i = 0; i < NumRegChannel; i ++ ){
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, i, 0xAAAA);
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}
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}
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if( ret != 0 ) { printf("!!!!!!!! set channels error.\n");}
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AutoSetDPPEventAggregation();
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if( ch >= 0 ){
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isSettingFilledinMemeory = false;
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usleep(1000*300);
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ReadAllSettingsFromBoard();
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}
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return ret;
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}
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int Digitizer::ProgramBoard_PSD(){
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DebugPrint("%s", "Digitizer");
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printf("===== Digitizer::%s\n", __func__);
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//ret = CAEN_DGTZ_Reset(handle);
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Reset();
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//ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0F0115); /// has Extra2, dual trace, input and CFD
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0E0115); /// has Extra2, no trace
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ret = CAEN_DGTZ_SetAcquisitionMode(handle, CAEN_DGTZ_SW_CONTROLLED); /// software command
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ret |= CAEN_DGTZ_SetIOLevel(handle, CAEN_DGTZ_IOLevel_NIM);
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ret |= CAEN_DGTZ_SetExtTriggerInputMode(handle, CAEN_DGTZ_TRGMODE_ACQ_ONLY);
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ret |= CAEN_DGTZ_SetChannelEnableMask(handle, 0xFFFF);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x0, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x1, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x2, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x3, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x4, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x5, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x6, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x7, 0xAAAA);
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if( ModelType == ModelTypeCode::VME ){
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x8, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0x9, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xA, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xB, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xC, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xD, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xE, 0xAAAA);
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, 0xF, 0xAAAA);
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}
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PSD::DPPAlgorithmControl2_G) + 0x7000 , 0x00000200 ); // use fine time
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::DPPAlgorithmControl) + 0x7000 , 0x00100003 ); // baseline 16 sample, 320fC
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PSD::TriggerThreshold) + 0x7000 , 100 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PreTrigger) + 0x7000 , 20 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::RecordLength_G) + 0x7000 , 80 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PSD::ShortGateWidth) + 0x7000 , 32 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PSD::LongGateWidth) + 0x7000 , 64 );
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ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::PSD::GateOffset) + 0x7000 , 19 );
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if( ret != 0 ) { printf("!!!!!!!! set channels error.\n");}
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//*========================== Board
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/// change address 0xEF08 (5 bits), this will reflected in the 2nd word of the Board Agg. header.
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardID, (DPPType & 0xF));
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//WriteRegister(DPP::BoardID, (DPPType & 0xF));
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AutoSetDPPEventAggregation();
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//ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0F0115); /// has Extra2, dual trace, input and CFD
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ret |= CAEN_DGTZ_WriteRegister(handle, DPP::BoardConfiguration, 0x0E0115); /// has Extra2, no trace
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ret |= CAEN_DGTZ_SetAcquisitionMode(handle, CAEN_DGTZ_SW_CONTROLLED); /// software command
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ret |= CAEN_DGTZ_SetIOLevel(handle, CAEN_DGTZ_IOLevel_NIM);
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ret |= CAEN_DGTZ_SetExtTriggerInputMode(handle, CAEN_DGTZ_TRGMODE_ACQ_ONLY);
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ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(DPP::GlobalTriggerMask), 0x0);
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ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(DPP::FrontPanelTRGOUTEnableMask), 0x0);
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ret |= CAEN_DGTZ_SetChannelEnableMask(handle, 0xFFFF);
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//*========================== Group
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ProgramChannel_PSD(-1);
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isSettingFilledinMemeory = false; /// unlock the ReadAllSettingsFromBoard();
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usleep(1000*300);
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ReadAllSettingsFromBoard();
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return ret;
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}
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int Digitizer::ProgramChannel_PSD(short ch){
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DebugPrint("%s", "Digitizer");
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printf("===== Digitizer::%s|ch:%d\n", __func__,ch);
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uint32_t channel = (ch << 8);
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if( ch < 0 ) channel = 0x7000;
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uint32_t address = (ch << 8);
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address = channel + DPP::PSD::DPPAlgorithmControl2_G; ret = CAEN_DGTZ_WriteRegister(handle, address, 0x00000200 ); // use fine time
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address = channel + DPP::DPPAlgorithmControl; ret |= CAEN_DGTZ_WriteRegister(handle, address, 0x00100003 ); // baseline 16 sample, 320fC
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address = channel + DPP::PSD::TriggerThreshold; ret |= CAEN_DGTZ_WriteRegister(handle, address, 100 );
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address = channel + DPP::PreTrigger; ret |= CAEN_DGTZ_WriteRegister(handle, address, 20 );
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address = channel + DPP::RecordLength_G; ret |= CAEN_DGTZ_WriteRegister(handle, address, 80 );
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address = channel + DPP::PSD::ShortGateWidth; ret |= CAEN_DGTZ_WriteRegister(handle, address, 32 );
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address = channel + DPP::PSD::LongGateWidth; ret |= CAEN_DGTZ_WriteRegister(handle, address, 64 );
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address = channel + DPP::PSD::GateOffset; ret |= CAEN_DGTZ_WriteRegister(handle, address, 19 );
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if( ch >= 0 ) {
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, ch, 0xAAAA);
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}else{
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for( int i = 0; i < NumRegChannel; i ++ ){
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ret |= CAEN_DGTZ_SetChannelDCOffset(handle, i, 0xAAAA);
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}
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}
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if( ret != 0 ) { printf("!!!!!!!! set channels error.\n");}
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AutoSetDPPEventAggregation();
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if( ch >= 0 ){
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isSettingFilledinMemeory = false;
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usleep(1000*300);
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ReadAllSettingsFromBoard();
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}
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return ret;
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}
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int Digitizer::ProgramBoard_QDC(){
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DebugPrint("%s", "Digitizer");
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printf("===== Digitizer::%s\n", __func__);
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Reset();
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int ret = 0;
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//*========================== Board
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/// change address 0xEF08 (5 bits), this will reflected in the 2nd word of the Board Agg. header.
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardID, (DPPType & 0xF));
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//WriteRegister(DPP::BoardID, (DPPType & 0xF));
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//WriteRegister(DPP::QDC::NumberEventsPerAggregate, 0x10, -1);
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WriteRegister(DPP::QDC::RecordLength_W, 16, -1); // 128 sample = 2048 ns
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WriteRegister(DPP::QDC::PreTrigger, 60, -1); // at 60 sample = 960 ns
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WriteRegister(DPP::QDC::GateWidth, 100/16, -1);
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WriteRegister(DPP::QDC::GateOffset, 0, -1);
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WriteRegister(DPP::QDC::FixedBaseline, 0, -1);
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//WriteRegister(DPP::QDC::DPPAlgorithmControl, 0x300112); // with test pulse, positive
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//WriteRegister(DPP::QDC::DPPAlgorithmControl, 0x300102); // No test pulse, positive
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WriteRegister(DPP::QDC::DPPAlgorithmControl, 0x310102); // No test pulse, negative
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WriteRegister(DPP::QDC::TriggerHoldOffWidth, 100/16, -1);
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WriteRegister(DPP::QDC::TRGOUTWidth, 100/16, -1);
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//WriteRegister(DPP::QDC::OverThresholdWidth, 100/16, -1);
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WriteRegister(DPP::QDC::SubChannelMask, 0xFF, -1);
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WriteRegister(DPP::QDC::DCOffset, 0xAAAA, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub0, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub1, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub2, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub3, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub4, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub5, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub6, 100, -1);
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WriteRegister(DPP::QDC::TriggerThreshold_sub7, 100, -1);
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WriteRegister(DPP::BoardConfiguration, 0xE0110);
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//WriteRegister(DPP::AggregateOrganization, 0x0);
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//WriteRegister(DPP::MaxAggregatePerBlockTransfer, 100);
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@ -512,18 +504,55 @@ int Digitizer::ProgramBoard_QDC(){
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WriteRegister(DPP::FrontPanelIOControl, 0x0);
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WriteRegister(DPP::QDC::GroupEnableMask, 0xFF);
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/// change address 0xEF08 (5 bits), this will reflected in the 2nd word of the Board Agg. header.
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ret = CAEN_DGTZ_WriteRegister(handle, DPP::BoardID, (DPPType & 0xF));
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//WriteRegister(DPP::BoardID, (DPPType & 0xF));
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//*========================== Group
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ProgramChannel_QDC(-1);
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isSettingFilledinMemeory = false; /// unlock the ReadAllSettingsFromBoard();
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usleep(1000*300);
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ReadAllSettingsFromBoard();
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return ret;
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}
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int Digitizer::ProgramChannel_QDC(short group){
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printf("===== Digitizer::%s|ch:%d\n", __func__,group);
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WriteRegister(DPP::QDC::PreTrigger, 60, group); // at 60 sample = 960 ns
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WriteRegister(DPP::QDC::GateWidth, 100/16, group);
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WriteRegister(DPP::QDC::GateOffset, 0, group);
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WriteRegister(DPP::QDC::FixedBaseline, 0, group);
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//WriteRegister(DPP::QDC::DPPAlgorithmControl, 0x300112); // with test pulse, positive
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//WriteRegister(DPP::QDC::DPPAlgorithmControl, 0x300102); // No test pulse, positive
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WriteRegister(DPP::QDC::DPPAlgorithmControl, 0x310102); // No test pulse, negative
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WriteRegister(DPP::QDC::TriggerHoldOffWidth, 100/16, group);
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WriteRegister(DPP::QDC::TRGOUTWidth, 100/16, group);
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//WriteRegister(DPP::QDC::OverThresholdWidth, 100/16, group);
|
||||
WriteRegister(DPP::QDC::SubChannelMask, 0xFF, group);
|
||||
|
||||
WriteRegister(DPP::QDC::DCOffset, 0xAAAA, group);
|
||||
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub0, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub1, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub2, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub3, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub4, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub5, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub6, 100, group);
|
||||
WriteRegister(DPP::QDC::TriggerThreshold_sub7, 100, group);
|
||||
|
||||
AutoSetDPPEventAggregation();
|
||||
|
||||
isSettingFilledinMemeory = false; /// unlock the ReadAllSettingsFromBoard();
|
||||
if( group >= 0 ){
|
||||
isSettingFilledinMemeory = false;
|
||||
usleep(1000*300);
|
||||
ReadAllSettingsFromBoard();
|
||||
}
|
||||
|
||||
usleep(1000*300);
|
||||
ReadAllSettingsFromBoard();
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
//========================================================= ACQ control
|
||||
|
|
|
|||
|
|
@ -73,6 +73,10 @@ class Digitizer{
|
|||
int ProgramBoard_PSD() ;
|
||||
int ProgramBoard_QDC() ;
|
||||
|
||||
int ProgramChannel_PHA(short ch) ; /// program a default PHA Channel for Si-detector, ch = -1 for all channel
|
||||
int ProgramChannel_PSD(short ch) ; /// program a default PSD Channel for Si-detector, ch = -1 for all channel
|
||||
int ProgramChannel_QDC(short group) ; /// program a default QDC group for Si-detector, ch = -1 for all group
|
||||
|
||||
public:
|
||||
Digitizer(); /// no digitizer open
|
||||
Digitizer(int boardID, int portID = 0, bool program = false, bool verbose = false);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user