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add some for DPP-QDC, not much

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This commit is contained in:
splitPoleDAQ 2023-06-20 16:18:02 -04:00
parent e540abb3fa
commit ef108a7855
5 changed files with 55 additions and 9 deletions
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3
.vscode/settings.json vendored
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@ -155,6 +155,7 @@
"qthread": "cpp",
"qrandomgenerator": "cpp",
"source_location": "cpp",
"splitpole.C": "cpp"
"splitpole.C": "cpp",
"forward_list": "cpp"
}
}

16
ClassDigitizer.cpp
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@ -105,6 +105,7 @@ int Digitizer::OpenDigitizer(int boardID, int portID, bool program, bool verbose
switch(BoardInfo.Model){
case CAEN_DGTZ_V1730: tick2ns = 2.0; break; ///ns -> 500 MSamples/s
case CAEN_DGTZ_V1725: tick2ns = 4.0; break; ///ns -> 250 MSamples/s
case CAEN_DGTZ_V1740: tick2ns = 16.0; break; ///ns -> 62.5 MSamples/s
default : tick2ns = 4.0; break;
}
data->tick2ns = tick2ns;
@ -353,7 +354,7 @@ int Digitizer::ProgramPSDBoard(){
ret |= CAEN_DGTZ_SetIOLevel(handle, CAEN_DGTZ_IOLevel_NIM);
ret |= CAEN_DGTZ_SetExtTriggerInputMode(handle, CAEN_DGTZ_TRGMODE_ACQ_ONLY);
ret = CAEN_DGTZ_SetChannelEnableMask(handle, 0xFFFF);
ret |= CAEN_DGTZ_SetChannelEnableMask(handle, 0xFFFF);
ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(DPP::ChannelDCOffset) + 0x7000 , 0xEEEE );
@ -371,6 +372,19 @@ int Digitizer::ProgramPSDBoard(){
return ret;
}
int Digitizer::ProgramQDCBoard(){
printf("===== Digitizer::%s\n", __func__);
Reset();
ret = CAEN_DGTZ_SetChannelEnableMask(handle, 0xFFFF);
isSettingFilledinMemeory = false; /// unlock the ReadAllSettingsFromBoard();
ReadAllSettingsFromBoard();
return ret;
}
//========================================================= ACQ control
void Digitizer::StartACQ(){
if ( AcqRun ) return;

1
ClassDigitizer.h
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@ -78,6 +78,7 @@ class Digitizer{
virtual int ProgramBoard() ; /// program a generic board, no program channel
int ProgramPHABoard() ; /// program a default PHA board with dual trace
int ProgramPSDBoard() ;
int ProgramQDCBoard() ;
//^================ ACQ control
void StopACQ();

39
RegisterAddress.h
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@ -371,6 +371,9 @@ namespace DPP {
{"64 samples", 2},
{"256 samples", 3},
{"1024 samples", 4}};
}
namespace Bit_DPPAlgorithmControl_QDC {
}
@ -730,11 +733,22 @@ namespace DPP {
}
namespace QDC {
const Reg GateWidth ("GateWidth" , 0x1030, RW::ReadWrite, false, 0xFFF, 4); /// R/W
const Reg GateOffset ("GateOfset" , 0x1034, RW::ReadWrite, false, 0xFF, 4); /// R/W
const Reg FixedBaseline ("FixedBaseline" , 0x1038, RW::ReadWrite, false, 0xFFF, 4); /// R/W
const Reg Pretrigger ("PreTrigger" , 0x103C, RW::ReadWrite, false, 0xFF, 4); /// R/W
const Reg DPPAlgorithmControl ("DPPAlgorithmControl" , 0x1040, RW::ReadWrite, false, {}); /// R/W
const Reg GateWidth_G ("GateWidth" , 0x1030, RW::ReadWrite, true, 0xFFF, 1); /// R/W
const Reg GateOffset_G ("GateOfset" , 0x1034, RW::ReadWrite, true, 0xFF, 1); /// R/W
const Reg FixedBaseline_G ("FixedBaseline" , 0x1038, RW::ReadWrite, true, 0xFFF, 1); /// R/W
const Reg Pretrigger_G ("PreTrigger" , 0x103C, RW::ReadWrite, true, 0xFF, 1); /// R/W
const Reg DPPAlgorithmControl_G ("DPPAlgorithmControl" , 0x1040, RW::ReadWrite, true, {}); /// R/W
const Reg TriggerHoldOffWidth_G ("Trigger Hold-off width" , 0x1074, RW::ReadWrite, true, 0xFFFF, 1); /// R/W
const Reg GroupStatus_RG ("Group Status" , 0x1088, RW::ReadONLY, true, {}); /// R/
const Reg AMCFirmwareRevision_RG ("AMC firmware version" , 0x108C, RW::ReadONLY, true, {}); /// R/
const Reg DCOffset_G ("DC offset" , 0x1098, RW::ReadWrite, true, 0xFFFF, 1); /// R/W
const Reg ChannelMask_G ("Channel Group Mask" , 0x10A8, RW::ReadWrite, true, 0xFF, 1); /// R/W
const Reg DCOffset_LowCh_G ("DC offset for low ch." , 0x10C0, RW::ReadWrite, true, {}); /// R/W
const Reg DCOffset_HighCh_G ("DC offset for high ch." , 0x10C4, RW::ReadWrite, true, {}); /// R/W
const Reg TriggerThreshold_G ("Trigger Threshold" , 0x10D0, RW::ReadWrite, true, {}); /// R/W
const Reg NumberEventsPerAggregate ("Number of Events per Aggregate", 0x8020, RW::ReadWrite, false, 0x3FF, 1); /// R/W
const Reg RecordLength ("Record Length" , 0x8024, RW::ReadWrite, false, 0xFFF, 1); /// R/W
}
} // end of DPP namepace Register
@ -800,7 +814,22 @@ const std::vector<Reg> RegisterPSDList = {
};
const std::vector<Reg> RegisterQDCList = { //TODO
DPP::QDC::GateWidth_G,
DPP::QDC::GateOffset_G,
DPP::QDC::FixedBaseline_G,
DPP::QDC::Pretrigger_G,
DPP::QDC::DPPAlgorithmControl_G,
DPP::QDC::TriggerHoldOffWidth_G,
DPP::QDC::GroupStatus_RG,
DPP::QDC::AMCFirmwareRevision_RG,
DPP::QDC::DCOffset_G,
DPP::QDC::ChannelMask_G,
DPP::QDC::DCOffset_LowCh_G,
DPP::QDC::DCOffset_HighCh_G,
DPP::QDC::TriggerThreshold_G,
DPP::QDC::NumberEventsPerAggregate,
DPP::QDC::RecordLength
};

3
SplitPoleAnalyzer.h
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@ -28,8 +28,9 @@ public:
RedefineEventBuilder({0}); // only build for the 0-th digitizer, otherwise, it will build event accross all digitizers
tick2ns = digi[0]->GetTick2ns();
SetBackwardBuild(false, 500); // using normal building (acceding in time) or backward building, int the case of backward building, default events to be build is 100.
SetBackwardBuild(false, 100); // using normal building (acceding in time) or backward building, int the case of backward building, default events to be build is 100.
evtbder = GetEventBuilder();
evtbder->SetTimeWindow(500);
//========== use the influx from the Analyzer
influx = new InfluxDB("https://fsunuc.physics.fsu.edu/influx/");