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#ifndef DIGITIZER_PARAMETER_H
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#define DIGITIZER_PARAMETER_H
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#include <cstdlib>
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#include <string>
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#include <vector>
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enum ANSTYPE {NUM, STR, NONE};
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enum TYPE {CH, DIG, LVDS, VGA};
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enum RW { ReadOnly, WriteOnly, ReadWrite};
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//^==================== Register Class
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class Reg {
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private:
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std::string name;
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std::string value;
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TYPE type;
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RW readWrite; // true for read/write, false for read-only
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bool isCmd;
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ANSTYPE ansType;
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std::string answerUnit;
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std::vector<std::pair<std::string, std::string>> answer;
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public:
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Reg(){
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name = "";
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readWrite = RW::ReadWrite;
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type = TYPE::CH;
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isCmd = false;
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value = "";
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ansType = ANSTYPE::STR;
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answerUnit = "";
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answer.clear();
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}
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Reg(std::string para, RW readwrite,
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TYPE type = TYPE::CH,
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std::vector<std::pair<std::string,std::string>> answer = {},
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ANSTYPE ansType = ANSTYPE::STR,
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std::string ansUnit = "",
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bool isCmd = false){
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this->name = para;
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this->readWrite = readwrite;
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this->type = type;
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this->isCmd = isCmd;
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this->value = "";
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this->ansType = ansType;
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this->answer = answer;
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this->answerUnit = ansUnit;
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}
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~Reg(){};
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void SetValue(std::string sv) { this->value = sv;}
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std::string GetValue() const { return value;}
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RW ReadWrite() const {return readWrite;}
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TYPE GetType() const {return type;}
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ANSTYPE GetAnswerType() const {return ansType;}
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std::string GetUnit() const {return answerUnit;}
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std::vector<std::pair<std::string,std::string>> GetAnswers() const {return answer;}
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std::string GetPara() const {return name;}
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std::string GetFullPara(int ch_index = -1) const {
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switch (type){
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case TYPE::DIG:{
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if( isCmd){
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return "/cmd/" + name;
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}else{
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return "/par/" + name;
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}
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}; break;
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case TYPE::CH:{
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std::string haha = "/par/";
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if( isCmd ){
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haha = "/cmd/";
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}
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if( ch_index == -1 ){
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return "/ch/0..63" + haha + name;
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}else{
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return "/ch/" + std::to_string(ch_index) + haha + name;
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}
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}; break;
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case TYPE::LVDS:{
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if( ch_index == -1 ){
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return "/lvds/0..3/par/" + name;
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}else{
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return "/lvds/" + std::to_string(ch_index) + "/par/"+ name;
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}
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}; break;
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case TYPE::VGA: {
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if( ch_index == -1 ){
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return "/vga/0..3/par/" + name;
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}else{
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return "/vga/" + std::to_string(ch_index) + "/par/"+ name;
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}
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}; break;
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default:
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return "invalid"; break;
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}
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}
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operator std::string () const {return name;} // this allow Reg kaka("XYZ", true); std::string haha = kaka;
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};
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//^==================== Some digitizer parameters
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// To avoid typo
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namespace DIGIPARA{
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const unsigned short TraceStep = 8;
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namespace DIG{
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///============== read only
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const Reg CupVer ("CupVer", RW::ReadOnly, TYPE::DIG);
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const Reg FPGA_firmwareVersion ("FPGA_FwVer", RW::ReadOnly, TYPE::DIG);
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const Reg FirmwareType ("FwType", RW::ReadOnly, TYPE::DIG, {{"DPP_PHA", ""}, {"DPP_ZLE", ""}, {"DPP_PSD", ""}, {"DPP_DAW", ""}, {"DPP_OPEN", ""}, {"Scope", ""}});
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const Reg ModelCode ("ModelCode", RW::ReadOnly, TYPE::DIG);
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const Reg PBCode ("PBCode", RW::ReadOnly, TYPE::DIG);
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const Reg ModelName ("ModelName", RW::ReadOnly, TYPE::DIG);
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const Reg FromFactor ("FormFactor", RW::ReadOnly, TYPE::DIG, {{"0", "VME"}, {"1", "VME64X"}, {"2", "DT"}});
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const Reg FamilyCode ("FamilyCode", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg SerialNumber ("SerialNum", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg PCBrev_MB ("PCBrev_MB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg PCBrev_PB ("PCBrev_PB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg DPP_License ("License", RW::ReadOnly, TYPE::DIG);
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const Reg DPP_LicenseStatus ("LicenseStatus", RW::ReadOnly, TYPE::DIG);
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const Reg DPP_LicenseRemainingTime ("LicenseRemainingTime", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg NumberOfChannel ("NumCh", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "sec");
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const Reg ADC_bit ("ADC_Nbit", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg ADC_SampleRate ("ADC_SamplRate", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "MS/s");
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const Reg InputDynamicRange ("InputRange", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Vpp");
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const Reg InputType ("InputType", RW::ReadOnly, TYPE::DIG, {{"0","Singled ended"}, {"1", "Differential"}});
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const Reg InputImpedance ("Zin", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Ohm");
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const Reg IPAddress ("IPAddress", RW::ReadOnly, TYPE::DIG);
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const Reg NetMask ("Netmask", RW::ReadOnly, TYPE::DIG);
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const Reg Gateway ("Gateway", RW::ReadOnly, TYPE::DIG);
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const Reg LED_status ("LedStatus", RW::ReadOnly, TYPE::DIG);
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const Reg ACQ_status ("AcquisitionStatus", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "byte");
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const Reg MaxRawDataSize ("MaxRawDataSize", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensAirIn ("TempSensAirIn", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensAirOut ("TempSensAirOut", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensCore ("TempSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensFirstADC ("TempSensFirstADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensLastADC ("TempSensLastADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensHottestADC ("TempSensHottestADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC0 ("TempSensADC0", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC1 ("TempSensADC1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC2 ("TempSensADC2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC3 ("TempSensADC3", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC4 ("TempSensADC4", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC5 ("TempSensADC5", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC6 ("TempSensADC6", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC7 ("TempSensADC7", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7};
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const Reg TempSensDCDC ("TempSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg VInSensDCDC ("VInSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "V");
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const Reg VOutSensDCDC ("VOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "V");
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const Reg IOutSensDCDC ("IOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Amp");
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const Reg FreqSensCore ("FreqSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Hz");
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const Reg DutyCycleSensDCDC ("DutyCycleSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "%");
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const Reg SpeedSensFan1 ("SpeedSensFan1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "rpm");
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const Reg SpeedSensFan2 ("SpeedSensFan2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "rpm");
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const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG);
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const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG, {{"True", "No Error"}, {"False", "Error"}});
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///============= read write
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const Reg ClockSource ("ClockSource", RW::ReadWrite, TYPE::DIG, {{"Internal", "Internal Clock 62.5 MHz"},
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{"FPClkIn", "Front Panel Clock Input"}});
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const Reg IO_Level ("IOlevel", RW::ReadWrite, TYPE::DIG, {{"NIM", "NIM (0=0V, 1=-0.8V) "}, {"TTL", "TTL (0=0V, 1=3.3V)"}});
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const Reg StartSource ("StartSource", RW::ReadWrite, TYPE::DIG, {{"EncodedClkIn", "CLK-IN/SYNC"},
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{"SINlevel", "S-IN Level"},
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{"SINedge", "S-IN Edge"},
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{"SWcmd", "Software"},
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{"LVDS", "LVDS"}});
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const Reg GlobalTriggerSource ("GlobalTriggerSource", RW::ReadWrite, TYPE::DIG,{{"TrgIn", "TRG-IN" },
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{"SwTrg", "Software" },
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{"GPIO", "GPIO" },
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{"TestPulse", "Test Pulse" },
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{"LVDS", "LVDS"}});
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const Reg BusyInSource ("BusyInSource", RW::ReadWrite, TYPE::DIG, {{"Disabled","Disabled"},
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{"SIN", "SIN"},
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{"GPIO", "GPIO"},
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{"LVDS", "LVDS"}});
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//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
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const Reg EnableClockOutFrontPanel ("EnClockOutFP", RW::ReadWrite, TYPE::DIG, {{"True", "Enable"}, {"False", "Disabled"}});
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const Reg TrgOutMode ("TrgOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"TRGIN", "TRG-IN"},
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{"SwTrg", "Software Trigger"},
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{"LVDS", "LVDS"},
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{"Run", "Run Signal"},
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{"RefClk", "Reference Clock"},
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{"TestPulse", "Test Pulse"},
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{"Busy", "Busy Signal"},
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{"Fixed0", "0-level"},
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{"Fixed1", "1-level"},
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{"SyncIn", "SyncIn Signal"},
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{"SIN", "S-IN Signal"},
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{"GPIO", "GPIO Signal"},
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{"AccepTrg", "Acceped Trigger Signal"},
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{"TrgClk", "Trigger Clock"}});
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const Reg GPIOMode ("GPIOMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"TRGIN", "TRG-IN"},
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{"P0", "Back Plane"},
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{"SIN", "S-IN Signal"},
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{"LVDS", "LVDS Trigger"},
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{"SwTrg", "Software Trigger"},
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{"Run", "Run Signal"},
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{"RefClk", "Referece Clock"},
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{"TestPulse", "Test Pulse"},
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{"Busy", "Busy Signal"},
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{"Fixed0", "0-Level"},
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{"Fixed1", "1-Level"}});
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const Reg SyncOutMode ("SyncOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"SyncIn", "Sync-In Signal"},
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{"TestPulse", "Test Pulse"},
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{"IntClk", "Internal Clock 62.5MHz"},
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{"Run", "Run Signal"} });
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const Reg BoardVetoSource ("BoardVetoSource", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"SIN", "S-IN"},
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{"LVDS", "LVDS"},
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{"GPIO", "GPIO"},
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{"P0", "Back Plane"}});
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const Reg BoardVetoWidth ("BoardVetoWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"34359738360", ""}, {"1", ""}}, ANSTYPE::NUM, "ns");
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const Reg BoardVetoPolarity ("BoardVetoPolarity", RW::ReadWrite, TYPE::DIG, {{"ActiveHigh", "High"}, {"ActiveLow", "Low"}});
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const Reg RunDelay ("RunDelay", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"524280", ""}, {"1", ""}}, ANSTYPE::NUM, "ns");
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const Reg EnableAutoDisarmACQ ("EnAutoDisarmAcq", RW::ReadWrite, TYPE::DIG, {{"True", "Enabled"}, {"False", "Disabled"}});
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const Reg EnableDataReduction ("EnDataReduction", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
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const Reg EnableStatisticEvents ("EnStatEvents", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
|
2023-03-03 15:23:26 -05:00
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const Reg VolatileClockOutDelay ("VolatileClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}, {"74.074", ""}}, ANSTYPE::NUM, "ps");
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const Reg PermanentClockOutDelay ("PermanentClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}, {"74.074", ""}}, ANSTYPE::NUM, "ps");
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const Reg TestPulsePeriod ("TestPulsePeriod", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}, {"8", ""}}, ANSTYPE::NUM, "ns");
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const Reg TestPulseWidth ("TestPulseWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}, {"8", ""}}, ANSTYPE::NUM, "ns");
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const Reg TestPulseLowLevel ("TestPulseLowLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}, {"1", ""}}, ANSTYPE::NUM, "ns");
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const Reg TestPulseHighLevel ("TestPulseHighLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}, {"1", ""}}, ANSTYPE::NUM, "ns");
|
2023-02-22 20:07:39 -05:00
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const Reg ErrorFlagMask ("ErrorFlagMask", RW::ReadWrite, TYPE::DIG);
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const Reg ErrorFlagDataMask ("ErrorFlagDataMask", RW::ReadWrite, TYPE::DIG);
|
2023-02-24 19:21:27 -05:00
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const Reg DACoutMode ("DACoutMode", RW::ReadWrite, TYPE::DIG, {{"Static", "DAC fixed level"},
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{"ChInput", "From Channel"},
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{"ChSum", "Sum of all Channels"},
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{"OverThrSum", "Number of Channels triggered"},
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{"Ramp", "14-bit counter"},
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{"Sin5MHz", "5 MHz Sin wave"},
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{"Square", "Test Pulse"}});
|
2023-03-03 15:23:26 -05:00
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const Reg DACoutStaticLevel ("DACoutStaticLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"16383", ""}, {"1",""}}, ANSTYPE::NUM, "units");
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const Reg DACoutChSelect ("DACoutChSelect", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"64", ""}, {"1",""}}, ANSTYPE::NUM);
|
2023-02-24 19:21:27 -05:00
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const Reg EnableOffsetCalibration ("EnOffsetCalibration", RW::ReadWrite, TYPE::DIG, {{"True", "Applied Cali."}, {"False", "No Cali."}});
|
2023-02-08 17:35:04 -05:00
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/// ========== command
|
2023-02-24 19:21:27 -05:00
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const Reg Reset ("Reset", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
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const Reg ClearData ("ClearData", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // clear memory, setting not affected
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const Reg ArmACQ ("ArmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
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const Reg DisarmACQ ("DisarmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
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const Reg SoftwareStartACQ ("SwStartAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only when SwStart in StartSource
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const Reg SoftwareStopACQ ("SwStopAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // stop ACQ, whatever start source
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const Reg SendSoftwareTrigger ("SendSWTrigger", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only work when Swtrg in the GlobalTriggerSource
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const Reg ReloadCalibration ("ReloadCalibration", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
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2023-02-08 17:35:04 -05:00
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const std::vector<Reg> AllSettings = {
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CupVer ,
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FPGA_firmwareVersion ,
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FirmwareType ,
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ModelCode ,
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PBCode ,
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ModelName ,
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FromFactor ,
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FamilyCode ,
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SerialNumber ,
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PCBrev_MB ,
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PCBrev_PB ,
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DPP_License ,
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DPP_LicenseStatus ,
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DPP_LicenseRemainingTime ,
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NumberOfChannel ,
|
2023-02-23 16:08:47 -05:00
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ADC_bit ,
|
2023-02-08 17:35:04 -05:00
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ADC_SampleRate ,
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InputDynamicRange ,
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InputType ,
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InputImpedance ,
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IPAddress ,
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NetMask ,
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Gateway ,
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LED_status ,
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ACQ_status ,
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MaxRawDataSize ,
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TempSensAirIn ,
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TempSensAirOut ,
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TempSensCore ,
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TempSensFirstADC ,
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TempSensLastADC ,
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TempSensHottestADC ,
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TempSensADC0 ,
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TempSensADC1 ,
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TempSensADC2 ,
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TempSensADC3 ,
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TempSensADC4 ,
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TempSensADC5 ,
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TempSensADC6 ,
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TempSensADC7 ,
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TempSensDCDC ,
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VInSensDCDC ,
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VOutSensDCDC ,
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IOutSensDCDC ,
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FreqSensCore ,
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DutyCycleSensDCDC ,
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SpeedSensFan1 ,
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SpeedSensFan2 ,
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ErrorFlags ,
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BoardReady ,
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ClockSource ,
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IO_Level ,
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StartSource ,
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GlobalTriggerSource ,
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BusyInSource ,
|
2023-02-22 20:07:39 -05:00
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//EnableClockOutBackplane ,
|
2023-02-08 17:35:04 -05:00
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EnableClockOutFrontPanel ,
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TrgOutMode ,
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GPIOMode ,
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SyncOutMode ,
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BoardVetoSource ,
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BoardVetoWidth ,
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BoardVetoPolarity ,
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RunDelay ,
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|
|
EnableAutoDisarmACQ ,
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|
|
EnableDataReduction ,
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|
|
EnableStatisticEvents ,
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|
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VolatileClockOutDelay ,
|
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|
|
PermanentClockOutDelay ,
|
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|
|
TestPulsePeriod ,
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TestPulseWidth ,
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|
TestPulseLowLevel ,
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TestPulseHighLevel ,
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ErrorFlagMask ,
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ErrorFlagDataMask ,
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DACoutMode ,
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|
|
DACoutStaticLevel ,
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DACoutChSelect ,
|
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EnableOffsetCalibration
|
|
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|
|
};
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|
|
}
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|
|
namespace VGA{
|
2023-03-03 15:23:26 -05:00
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|
const Reg VGAGain ("VGAGain", RW::ReadWrite, TYPE::VGA, {{"0", ""},{"40", ""}, {"0.5",""}}, ANSTYPE::NUM, "dB"); // VX2745 only
|
2023-02-08 17:35:04 -05:00
|
|
|
}
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|
|
|
namespace CH{
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|
/// ========= red only
|
2023-02-24 19:21:27 -05:00
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|
const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::NUM, "Hz");
|
2023-02-08 17:35:04 -05:00
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|
const Reg ChannelStatus ("ChStatus", RW::ReadOnly);
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|
const Reg GainFactor ("GainFactor", RW::ReadOnly);
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|
|
const Reg ADCToVolts ("ADCToVolts", RW::ReadOnly);
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|
|
const Reg Energy_Nbit ("Energy_Nbit", RW::ReadOnly);
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|
|
const Reg ChannelRealtime ("ChRealtimeMonitor", RW::ReadOnly); // when called, update DeadTime, TriggerCount, SaveCount, and WaveCount
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|
|
const Reg ChannelDeadtime ("ChDeadtimeMonitor", RW::ReadOnly);
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|
const Reg ChannelTriggerCount ("ChTriggerCnt", RW::ReadOnly);
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|
|
const Reg ChannelSavedCount ("ChSavedEventCnt", RW::ReadOnly);
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|
|
const Reg ChannelWaveCount ("ChWaveCnt", RW::ReadOnly);
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|
|
/// ======= read write
|
2023-02-24 19:21:27 -05:00
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|
|
const Reg ChannelEnable ("ChEnable", RW::ReadWrite, TYPE::CH, {{"True", "Enabled"}, {"False", "Disabled"}});
|
2023-03-03 15:23:26 -05:00
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|
|
const Reg DC_Offset ("DCOffset", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"100", ""}, {"1",""}}, ANSTYPE::NUM, "%");
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|
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|
|
const Reg TriggerThreshold ("TriggerThr", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8191", ""}, {"1",""}}, ANSTYPE::NUM);
|
2023-02-24 19:21:27 -05:00
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|
|
const Reg Polarity ("PulsePolarity", RW::ReadWrite, TYPE::CH, {{"Positive", "Pos. +"},{"Negative", "Neg. -"}});
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|
|
const Reg WaveDataSource ("WaveDataSource", RW::ReadWrite, TYPE::CH, {{"ADC_DATA", "Input ADC"},
|
|
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|
|
{"ADC_TEST_TOGGLE", "ADC produces TOGGLE signal"},
|
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|
|
{"ADC_TEST_RAMP", "ADC produces RAMP signal"},
|
|
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|
|
{"ADC_TEST_SIN", "ADC produce SIN signal"},
|
|
|
|
|
{"Ramp", "Ramp generator"},
|
|
|
|
|
{"SquareWave", "Test Pusle (Square Wave)"} });
|
2023-03-03 15:23:26 -05:00
|
|
|
const Reg RecordLength ("ChRecordLengthT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"64800", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
|
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|
|
const Reg PreTrigger ("ChPreTriggerT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"32000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
2023-02-24 19:21:27 -05:00
|
|
|
const Reg WaveSaving ("WaveSaving", RW::ReadWrite, TYPE::CH, {{"Always", "Always"}, {"OnRequest", "On Request"}});
|
2023-03-02 15:00:59 -05:00
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|
|
const Reg WaveResolution ("WaveResolution", RW::ReadWrite, TYPE::CH, {{"RES8", " 8 ns"},
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|
|
{"RES16","16 ns"},
|
|
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|
|
{"RES32","32 ns"},
|
|
|
|
|
{"RES64","64 ns"}});
|
2023-03-03 15:23:26 -05:00
|
|
|
const Reg TimeFilterRiseTime ("TimeFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"2000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
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|
|
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
|
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|
|
const Reg EnergyFilterRiseTime ("EnergyFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"13000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
|
|
|
|
const Reg EnergyFilterFlatTop ("EnergyFilterFlatTopT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"3000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
|
|
|
|
const Reg EnergyFilterPoleZero ("EnergyFilterPoleZeroT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"524000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
|
|
|
|
const Reg EnergyFilterPeakingPosition ("EnergyFilterPeakingPosition", RW::ReadWrite, TYPE::CH, {{"0", ""},{"100", ""}, {"1",""}}, ANSTYPE::NUM, "%");
|
2023-02-28 13:28:30 -05:00
|
|
|
const Reg EnergyFilterPeakingAvg ("EnergyFilterPeakingAvg", RW::ReadWrite, TYPE::CH, {{"OneShot", "1 sample"},
|
|
|
|
|
{"LowAVG", "4 samples"},
|
2023-02-24 19:21:27 -05:00
|
|
|
{"MediumAVG", "16 samples"},
|
|
|
|
|
{"HighAVG", "64 samples"}});
|
2023-02-28 13:28:30 -05:00
|
|
|
const Reg EnergyFilterBaselineAvg ("EnergyFilterBaselineAvg", RW::ReadWrite, TYPE::CH, {{"Fixed", "0 sample"},
|
|
|
|
|
{"VeryLow", "16 samples"},
|
|
|
|
|
{"Low", "64 samples"},
|
|
|
|
|
{"MediumLow", "256 samples"},
|
|
|
|
|
{"Medium", "1024 samples"},
|
|
|
|
|
{"MediumHigh","4096 samples"},
|
2023-02-24 19:21:27 -05:00
|
|
|
{"High", "16384 samples"}});
|
2023-03-03 15:23:26 -05:00
|
|
|
const Reg EnergyFilterBaselineGuard ("EnergyFilterBaselineGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}, {"8",""}}, ANSTYPE::NUM, "ns");
|
|
|
|
|
const Reg EnergyFilterFineGain ("EnergyFilterFineGain", RW::ReadWrite, TYPE::CH, {{"0", ""},{"10", ""}, {"0.001",""}}, ANSTYPE::NUM);
|
|
|
|
|
const Reg EnergyFilterPileUpGuard ("EnergyFilterPileUpGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"64000", ""}, {"8",""}}, ANSTYPE::NUM);
|
2023-03-02 15:00:59 -05:00
|
|
|
const Reg EnergyFilterLowFreqFilter ("EnergyFilterLFLimitation", RW::ReadWrite, TYPE::CH, {{"Off", "Disabled"}, {"On", "Enabled"}});
|
2023-02-24 19:21:27 -05:00
|
|
|
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
|
|
|
|
|
{"TimeFilter", "Time Filter"},
|
|
|
|
|
{"EnergyFilter", "Trapazoid"},
|
|
|
|
|
{"EnergyFilterBase", "Trap. Baseline"},
|
|
|
|
|
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
|
|
|
|
|
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
|
|
|
|
|
{"TimeFilter", "Time Filter"},
|
|
|
|
|
{"EnergyFilter", "Trapazoid"},
|
|
|
|
|
{"EnergyFilterBase", "Trap. Baseline"},
|
|
|
|
|
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
|
|
|
|
|
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
|
|
|
|
{"TimeFilterArmed", "Time Filter Armed"},
|
|
|
|
|
{"ReTriggerGuard", "ReTrigger Guard"},
|
|
|
|
|
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
|
|
|
|
{"EnergyFilterPeaking", "Peaking"},
|
|
|
|
|
{"EnergyFilterPeakReady", "Peak Ready"},
|
|
|
|
|
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
|
|
|
|
{"EventPileUp", "Event Pile Up"},
|
|
|
|
|
{"ADCSaturation", "ADC Saturate"},
|
|
|
|
|
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
|
|
|
|
{"PostSaturationEvent", "Post Sat. Event"},
|
|
|
|
|
{"EnergylterSaturation", "Trap. Saturate"},
|
|
|
|
|
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
|
|
|
|
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
|
|
|
|
{"TimeFilterArmed", "Time Filter Armed"},
|
|
|
|
|
{"ReTriggerGuard", "ReTrigger Guard"},
|
|
|
|
|
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
|
|
|
|
{"EnergyFilterPeaking", "Peaking"},
|
|
|
|
|
{"EnergyFilterPeakReady", "Peak Ready"},
|
|
|
|
|
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
|
|
|
|
{"EventPileUp", "Event Pile Up"},
|
|
|
|
|
{"ADCSaturation", "ADC Saturate"},
|
|
|
|
|
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
|
|
|
|
{"PostSaturationEvent", "Post Sat. Event"},
|
|
|
|
|
{"EnergylterSaturation", "Trap. Saturate"},
|
|
|
|
|
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
|
|
|
|
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
|
|
|
|
{"TimeFilterArmed", "Time Filter Armed"},
|
|
|
|
|
{"ReTriggerGuard", "ReTrigger Guard"},
|
|
|
|
|
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
|
|
|
|
{"EnergyFilterPeaking", "Peaking"},
|
|
|
|
|
{"EnergyFilterPeakReady", "Peak Ready"},
|
|
|
|
|
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
|
|
|
|
{"EventPileUp", "Event Pile Up"},
|
|
|
|
|
{"ADCSaturation", "ADC Saturate"},
|
|
|
|
|
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
|
|
|
|
{"PostSaturationEvent", "Post Sat. Event"},
|
|
|
|
|
{"EnergylterSaturation", "Trap. Saturate"},
|
|
|
|
|
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
|
|
|
|
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
|
|
|
|
{"TimeFilterArmed", "Time Filter Armed"},
|
|
|
|
|
{"ReTriggerGuard", "ReTrigger Guard"},
|
|
|
|
|
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
|
|
|
|
{"EnergyFilterPeaking", "Peaking"},
|
|
|
|
|
{"EnergyFilterPeakReady", "Peak Ready"},
|
|
|
|
|
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
|
|
|
|
{"EventPileUp", "Event Pile Up"},
|
|
|
|
|
{"ADCSaturation", "ADC Saturate"},
|
|
|
|
|
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
|
|
|
|
{"PostSaturationEvent", "Post Sat. Event"},
|
|
|
|
|
{"EnergylterSaturation", "Trap. Saturate"},
|
|
|
|
|
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
2023-02-08 17:35:04 -05:00
|
|
|
|
|
|
|
|
const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1};
|
|
|
|
|
const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3};
|
|
|
|
|
|
2023-02-24 19:21:27 -05:00
|
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const Reg EventTriggerSource ("EventTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
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{"TRGIN", "TRG-IN"},
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{"SWTrigger", "Software Trigger"},
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{"ChSelfTrigger", "Channel Self-Trigger"},
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{"Ch64Trigger", "Channel 64-Trigger"},
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{"Disabled", "Disabled"}});
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const Reg ChannelsTriggerMask ("ChannelsTriggerMask", RW::ReadWrite, TYPE::CH, {}, ANSTYPE::STR, "64-bit" );
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const Reg ChannelVetoSource ("ChannelVetoSource", RW::ReadWrite, TYPE::CH, {{"BoardVeto", "Board Veto"},
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{"ADCOverSaturation", "ADC Over Saturation"},
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2023-03-02 18:18:02 -05:00
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{"ADCUnderSaturation", "ADC Under Saturation"},
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{"Disabled", "Disabled"}});
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2023-02-24 19:21:27 -05:00
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const Reg WaveTriggerSource ("WaveTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
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{"TRGIN", "TRG-IN"},
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{"ExternalInhibit", "External Inhibit"},
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{"ADCUnderSaturation", "ADC Under Saturation"},
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{"ADCOverSaturation", "ADC Over Saturation"},
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{"SWTrigger", "Software Trigger"},
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{"ChSelfTrigger", "Channel Self-Trigger"},
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{"Ch64Trigger", "Channel 64-Trigger"},
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{"Disabled", "Disabled"}});
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const Reg EventSelector ("EventSelector", RW::ReadWrite, TYPE::CH, {{"All", "All"},
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{"Pileup", "Pile up"},
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{"EnergySkim", "Energy Skim"}});
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const Reg WaveSelector ("WaveSelector", RW::ReadWrite, TYPE::CH, {{"All", "All wave"},
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{"Pileup", "Only Pile up"},
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{"EnergySkim", "Only in Energy Skim Range"}});
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2023-03-02 18:18:02 -05:00
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const Reg CoincidenceMask ("CoincidenceMask", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},
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2023-02-24 19:21:27 -05:00
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{"Ch64Trigger", "Channel 64-Trigger"},
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{"TRGIN", "TRG-IN"},
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{"GlobalTriggerSource", "Global Trigger"},
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{"ITLA", "ITLA"},
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{"ITLB", "ITLB"}});
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2023-03-02 18:18:02 -05:00
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const Reg AntiCoincidenceMask ("AntiCoincidenceMask", RW::ReadWrite, TYPE::CH,{{"Disabled", "Disabled"},
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2023-02-24 19:21:27 -05:00
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{"Ch64Trigger", "Channel 64-Trigger"},
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{"TRGIN", "TRG-IN"},
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{"GlobalTriggerSource", "Global Trigger"},
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{"ITLA", "ITLA"},
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{"ITLB", "ITLB"}});
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2023-03-03 15:23:26 -05:00
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const Reg CoincidenceLength ("CoincidenceLengthT", RW::ReadWrite, TYPE::CH, {{"8", ""},{"524280", ""}, {"8", ""}}, ANSTYPE::NUM, "ns");
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2023-02-08 17:35:04 -05:00
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const Reg CoincidenceLengthSample ("CoincidenceLengthS", RW::ReadWrite);
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2023-03-03 15:23:26 -05:00
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const Reg ADCVetoWidth ("ADCVetoWidth", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"524280", ""}, {"1", ""}}, ANSTYPE::NONE, "ns");
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2023-02-08 17:35:04 -05:00
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2023-03-03 15:23:26 -05:00
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const Reg EnergySkimLowDiscriminator ("EnergySkimLowDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}, {"1", ""}}, ANSTYPE::NUM);
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const Reg EnergySkimHighDiscriminator ("EnergySkimHighDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}, {"1", ""}}, ANSTYPE::NUM);
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2023-02-08 17:35:04 -05:00
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const Reg RecordLengthSample ("ChRecordLengthS", RW::ReadWrite);
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const Reg PreTriggerSample ("ChPreTriggerS", RW::ReadWrite);
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const Reg TimeFilterRiseTimeSample ("TimeFilterRiseTimeS", RW::ReadWrite);
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const Reg TimeFilterRetriggerGuardSample ("TimeFilterRetriggerGuardS", RW::ReadWrite);
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const Reg EnergyFilterRiseTimeSample ("EnergyFilterRiseTimeS", RW::ReadWrite);
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const Reg EnergyFilterFlatTopSample ("EnergyFilterFlatTopS", RW::ReadWrite);
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const Reg EnergyFilterPoleZeroSample ("EnergyFilterPoleZeroS", RW::ReadWrite);
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const Reg EnergyFilterBaselineGuardSample ("EnergyFilterBaselineGuardS", RW::ReadWrite);
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const Reg EnergyFilterPileUpGuardSample ("EnergyFilterPileUpGuardS", RW::ReadWrite);
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const std::vector<Reg> AllSettings = {
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SelfTrgRate ,
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ChannelStatus ,
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GainFactor ,
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ADCToVolts ,
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Energy_Nbit ,
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ChannelRealtime ,
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ChannelDeadtime ,
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ChannelTriggerCount ,
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ChannelSavedCount ,
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ChannelWaveCount ,
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ChannelEnable ,
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DC_Offset ,
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TriggerThreshold ,
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Polarity ,
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WaveDataSource ,
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RecordLength ,
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WaveSaving ,
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WaveResolution ,
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PreTrigger ,
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TimeFilterRiseTime ,
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TimeFilterRetriggerGuard ,
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EnergyFilterRiseTime ,
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EnergyFilterFlatTop ,
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EnergyFilterPoleZero ,
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EnergyFilterBaselineGuard ,
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EnergyFilterPileUpGuard ,
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EnergyFilterPeakingPosition,
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EnergyFilterPeakingAvg ,
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EnergyFilterFineGain ,
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EnergyFilterLowFreqFilter ,
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EnergyFilterBaselineAvg ,
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WaveAnalogProbe0 ,
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WaveAnalogProbe1 ,
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WaveDigitalProbe0 ,
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WaveDigitalProbe1 ,
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WaveDigitalProbe2 ,
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WaveDigitalProbe3 ,
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EventTriggerSource ,
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ChannelsTriggerMask ,
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ChannelVetoSource ,
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WaveTriggerSource ,
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EventSelector ,
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WaveSelector ,
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CoincidenceMask ,
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AntiCoincidenceMask ,
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CoincidenceLength ,
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CoincidenceLengthSample ,
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ADCVetoWidth ,
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EnergySkimLowDiscriminator ,
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EnergySkimHighDiscriminator,
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RecordLengthSample ,
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PreTriggerSample ,
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TimeFilterRiseTimeSample ,
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TimeFilterRetriggerGuardSample ,
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EnergyFilterRiseTimeSample ,
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EnergyFilterFlatTopSample ,
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EnergyFilterPoleZeroSample ,
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EnergyFilterBaselineGuardSample ,
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EnergyFilterPileUpGuardSample
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};
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}
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};
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#endif
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