added PSD prarmeeters
This commit is contained in:
parent
d7d3988b75
commit
71464484ba
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@ -283,6 +283,20 @@ void Digitizer2Gen::StopACQ(){
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acqON = false;
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}
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//================ Data Format
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//------- PHA
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// 0 = all
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// 1 = 1 trace
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// 2 = no trace
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// 3 = minimum (only energy and timestamp)
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// 15 = raw buffer
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//------- PSD
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//?? 4 = all
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//?? 5 = 1 trace
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//?? 6 = no trace
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//?? 7 = only energy + timestamp
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//?? 16 = raw buffer
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void Digitizer2Gen::SetPHADataFormat(unsigned short dataFormat){
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printf("%s : %d\n", __func__, dataFormat);
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@ -629,7 +643,7 @@ void Digitizer2Gen::SaveDataToFile(){
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//###########################################
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void Digitizer2Gen::Reset(){ SendCommand("/cmd/Reset"); }
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void Digitizer2Gen::ProgramPHABoard(){
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void Digitizer2Gen::ProgramDPPBoard(){
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if( !isConnected ) return ;
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//============= Board
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@ -687,12 +701,7 @@ void Digitizer2Gen::ProgramPHAChannels(bool testPulse){
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// Channel setting
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if( testPulse){
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WriteValue("/ch/0..63/par/ChEnable" , "false");
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WriteValue("/ch/0/par/ChEnable" , "true");
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WriteValue("/ch/1/par/ChEnable" , "true");
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WriteValue("/ch/2/par/ChEnable" , "true");
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WriteValue("/ch/3/par/ChEnable" , "true");
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//WriteValue("/ch/0..63/par/ChEnable" , "true");
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WriteValue("/ch/0..63/par/ChEnable" , "true");
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WriteValue("/ch/0..63/par/EventTriggerSource", "GlobalTriggerSource");
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WriteValue("/ch/0..63/par/WaveTriggerSource" , "GlobalTriggerSource"); // EventTriggerSource enought
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@ -707,7 +716,8 @@ void Digitizer2Gen::ProgramPHAChannels(bool testPulse){
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//======== Self trigger for each channel
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WriteValue("/ch/0..63/par/ChEnable" , "true");
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WriteValue("/ch/0..63/par/WaveAnalogProbe0" , "ADCInput");
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WriteValue("/ch/0..63/par/WaveDaatSource" , "ADC_DATA");
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WriteValue("/ch/0..63/par/WaveResolution" , "RES8"); /// 8 ns
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WriteValue("/ch/0..63/par/WaveSaving" , "OnRequest");
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WriteValue("/ch/0..63/par/PulsePolarity" , "Positive");
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@ -757,7 +767,44 @@ void Digitizer2Gen::ProgramPHAChannels(bool testPulse){
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WriteValue("/ch/0..63/par/ITLConnect" , "Disabled");
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}
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}
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void Digitizer2Gen::ProgramPSDChannels(bool testPulse){
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if( testPulse){
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WriteValue("/ch/0..63/par/ChEnable" , "false");
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WriteValue("/ch/0..63/par/ChEnable" , "true");
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WriteValue("/ch/0..63/par/EventTriggerSource", "GlobalTriggerSource");
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WriteValue("/ch/0..63/par/WaveTriggerSource" , "GlobalTriggerSource"); // EventTriggerSource enought
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WriteValue("/par/GlobalTriggerSource", "SwTrg | TestPulse");
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WriteValue("/par/TestPulsePeriod" , "1000000"); // 1.0 msec = 1000Hz, tested, 1 trace recording
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WriteValue("/par/TestPulseWidth" , "1000"); // nsec
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WriteValue("/par/TestPulseLowLevel" , "0");
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WriteValue("/par/TestPulseHighLevel" , "10000");
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}else{
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//TODO not finished.
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//======== Self trigger for each channel
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WriteValue("/ch/0..63/par/ChEnable" , "true");
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WriteValue("/ch/0..63/par/WaveDaatSource" , "ADC_DATA");
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WriteValue("/ch/0..63/par/WaveResolution" , "RES8"); /// 8 ns
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WriteValue("/ch/0..63/par/WaveSaving" , "OnRequest");
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WriteValue("/ch/0..63/par/PulsePolarity" , "Positive");
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WriteValue("/ch/0..63/par/DCOffset" , "20"); /// 20%
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WriteValue("/ch/0..63/par/TriggerThr" , "1000");
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WriteValue("/ch/0..63/par/EventNeutronReject", "Disabled");
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WriteValue("/ch/0..63/par/WaveNeutronReject", "Disabled");
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WriteValue("/ch/0..63/par/WaveAnalogProbe0" , "ADCInput");
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WriteValue("/ch/0..63/par/ChRecordLengthT" , "4096"); /// 4096 ns, S and T are not Sync
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WriteValue("/ch/0..63/par/ChPreTriggerT" , "1000"); /// 1000 ns
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}
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}
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@ -116,8 +116,9 @@ class Digitizer2Gen {
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uint64_t GetRealTime(int ch) const {return realTime[ch];}
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void Reset();
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void ProgramPHABoard();
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void ProgramDPPBoard();
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void ProgramPHAChannels(bool testPulse = false);
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void ProgramPSDChannels(bool testPulse = false);
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unsigned short GetNChannels() const {return nChannels;}
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unsigned short GetCh2ns() const {return ch2ns;}
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465
DigiParameters.h
465
DigiParameters.h
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@ -655,4 +655,469 @@ namespace PHA{
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};
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namespace PSD{
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namespace DIG{
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///============== read only
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const Reg CupVer = PHA::DIG::CupVer;
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const Reg FPGA_firmwareVersion = PHA::DIG::FPGA_firmwareVersion;
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const Reg FirmwareType = PHA::DIG::FirmwareType;
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const Reg ModelCode = PHA::DIG::ModelCode;
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const Reg PBCode = PHA::DIG::PBCode;
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const Reg ModelName = PHA::DIG::ModelName;
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const Reg FromFactor = PHA::DIG::FromFactor;
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const Reg FamilyCode = PHA::DIG::FamilyCode;
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const Reg SerialNumber = PHA::DIG::SerialNumber;
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const Reg PCBrev_MB = PHA::DIG::PCBrev_MB;
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const Reg PCBrev_PB = PHA::DIG::PCBrev_PB;
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const Reg DPP_License = PHA::DIG::DPP_License;
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const Reg DPP_LicenseStatus = PHA::DIG::DPP_LicenseStatus;
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const Reg DPP_LicenseRemainingTime = PHA::DIG::DPP_LicenseRemainingTime;
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const Reg NumberOfChannel = PHA::DIG::NumberOfChannel;
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const Reg ADC_bit = PHA::DIG::ADC_bit;
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const Reg ADC_SampleRate = PHA::DIG::ADC_SampleRate;
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const Reg InputDynamicRange = PHA::DIG::InputDynamicRange;
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const Reg InputType = PHA::DIG::InputType;
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const Reg InputImpedance = PHA::DIG::InputImpedance;
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const Reg IPAddress = PHA::DIG::IPAddress;
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const Reg NetMask = PHA::DIG::NetMask;
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const Reg Gateway = PHA::DIG::Gateway;
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const Reg LED_status = PHA::DIG::LED_status;
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const Reg ACQ_status = PHA::DIG::ACQ_status;
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const Reg MaxRawDataSize = PHA::DIG::MaxRawDataSize;
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const Reg TempSensAirIn = PHA::DIG::TempSensAirIn;
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const Reg TempSensAirOut = PHA::DIG::TempSensAirOut;
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const Reg TempSensCore = PHA::DIG::TempSensCore;
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const Reg TempSensFirstADC = PHA::DIG::TempSensFirstADC;
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const Reg TempSensLastADC = PHA::DIG::TempSensLastADC;
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const Reg TempSensHottestADC = PHA::DIG::TempSensHottestADC;
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const Reg TempSensADC0 = PHA::DIG::TempSensADC0;
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const Reg TempSensADC1 = PHA::DIG::TempSensADC1;
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const Reg TempSensADC2 = PHA::DIG::TempSensADC2;
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const Reg TempSensADC3 = PHA::DIG::TempSensADC3;
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const Reg TempSensADC4 = PHA::DIG::TempSensADC4;
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const Reg TempSensADC5 = PHA::DIG::TempSensADC5;
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const Reg TempSensADC6 = PHA::DIG::TempSensADC6;
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const Reg TempSensADC7 = PHA::DIG::TempSensADC7;
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const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7};
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const std::vector<Reg> TempSensOthers = {TempSensAirIn,TempSensAirOut,TempSensCore,TempSensFirstADC,TempSensLastADC,TempSensHottestADC};
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const Reg TempSensDCDC = PHA::DIG::TempSensDCDC;
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const Reg VInSensDCDC = PHA::DIG::VInSensDCDC;
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const Reg VOutSensDCDC = PHA::DIG::VOutSensDCDC;
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const Reg IOutSensDCDC = PHA::DIG::IOutSensDCDC;
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const Reg FreqSensCore = PHA::DIG::FreqSensCore;
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const Reg DutyCycleSensDCDC = PHA::DIG::DutyCycleSensDCDC;
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const Reg SpeedSensFan1 = PHA::DIG::SpeedSensFan1;
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const Reg SpeedSensFan2 = PHA::DIG::SpeedSensFan2;
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const Reg ErrorFlags = PHA::DIG::ErrorFlags;
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const Reg BoardReady = PHA::DIG::BoardReady;
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///============= read write
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//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
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const Reg ClockSource = PHA::DIG::ClockSource;
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const Reg IO_Level = PHA::DIG::IO_Level;
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const Reg StartSource = PHA::DIG::StartSource;
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const Reg GlobalTriggerSource = PHA::DIG::GlobalTriggerSource;
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const Reg BusyInSource = PHA::DIG::BusyInSource;
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const Reg EnableClockOutFrontPanel = PHA::DIG::EnableClockOutFrontPanel;
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const Reg TrgOutMode = PHA::DIG::TrgOutMode;
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const Reg GPIOMode = PHA::DIG::GPIOMode;
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const Reg SyncOutMode = PHA::DIG::SyncOutMode;
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const Reg BoardVetoSource = PHA::DIG::BoardVetoSource;
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const Reg BoardVetoWidth = PHA::DIG::BoardVetoWidth;
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const Reg BoardVetoPolarity = PHA::DIG::BoardVetoPolarity;
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const Reg RunDelay = PHA::DIG::RunDelay;
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const Reg EnableAutoDisarmACQ = PHA::DIG::EnableAutoDisarmACQ;
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const Reg EnableDataReduction = PHA::DIG::EnableDataReduction;
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const Reg EnableStatisticEvents = PHA::DIG::EnableStatisticEvents;
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const Reg VolatileClockOutDelay = PHA::DIG::VolatileClockOutDelay;
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const Reg PermanentClockOutDelay = PHA::DIG::PermanentClockOutDelay;
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const Reg TestPulsePeriod = PHA::DIG::TestPulsePeriod;
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const Reg TestPulseWidth = PHA::DIG::TestPulseWidth;
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const Reg TestPulseLowLevel = PHA::DIG::TestPulseLowLevel;
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const Reg TestPulseHighLevel = PHA::DIG::TestPulseHighLevel;
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const Reg ErrorFlagMask = PHA::DIG::ErrorFlagMask;
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const Reg ErrorFlagDataMask = PHA::DIG::ErrorFlagDataMask;
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const Reg DACoutMode = PHA::DIG::DACoutMode;
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const Reg DACoutStaticLevel = PHA::DIG::DACoutStaticLevel;
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const Reg DACoutChSelect = PHA::DIG::DACoutChSelect;
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const Reg EnableOffsetCalibration = PHA::DIG::EnableOffsetCalibration;
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const Reg ITLAMainLogic = PHA::DIG::ITLAMainLogic;
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const Reg ITLAMajorityLev = PHA::DIG::ITLAMajorityLev;
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const Reg ITLAPairLogic = PHA::DIG::ITLAPairLogic;
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const Reg ITLAPolarity = PHA::DIG::ITLAPolarity;
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const Reg ITLAMask = PHA::DIG::ITLAMask;
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const Reg ITLAGateWidth = PHA::DIG::ITLAGateWidth;
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const Reg ITLBMainLogic = PHA::DIG::ITLBMainLogic;
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const Reg ITLBMajorityLev = PHA::DIG::ITLBMajorityLev;
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const Reg ITLBPairLogic = PHA::DIG::ITLBPairLogic;
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const Reg ITLBPolarity = PHA::DIG::ITLBPolarity;
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const Reg ITLBMask = PHA::DIG::ITLBMask;
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const Reg ITLBGateWidth = PHA::DIG::ITLBGateWidth;
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const Reg LVDSIOReg = PHA::DIG::LVDSIOReg;
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//const Reg LVDSTrgMask ("lvdstrgmask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BYTE, "64-bit");
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/// ========== command
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const Reg Reset = PHA::DIG::Reset;
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const Reg ClearData = PHA::DIG::ClearData;
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const Reg ArmACQ = PHA::DIG::ArmACQ;
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const Reg DisarmACQ = PHA::DIG::DisarmACQ;
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const Reg SoftwareStartACQ = PHA::DIG::SoftwareStartACQ;
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const Reg SoftwareStopACQ = PHA::DIG::SoftwareStopACQ;
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const Reg SendSoftwareTrigger = PHA::DIG::SendSoftwareTrigger;
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const Reg ReloadCalibration = PHA::DIG::ReloadCalibration;
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const std::vector<Reg> AllSettings = {
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CupVer ,
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FPGA_firmwareVersion ,
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FirmwareType ,
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ModelCode ,
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PBCode ,
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ModelName ,
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FromFactor ,
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FamilyCode ,
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SerialNumber ,
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PCBrev_MB ,
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PCBrev_PB ,
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DPP_License ,
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DPP_LicenseStatus ,
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DPP_LicenseRemainingTime ,
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NumberOfChannel ,
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ADC_bit ,
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ADC_SampleRate ,
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InputDynamicRange ,
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InputType ,
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InputImpedance ,
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IPAddress ,
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NetMask ,
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Gateway ,
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LED_status ,
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ACQ_status ,
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MaxRawDataSize ,
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TempSensAirIn ,
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TempSensAirOut ,
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TempSensCore ,
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TempSensFirstADC ,
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TempSensLastADC ,
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TempSensHottestADC ,
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TempSensADC0 ,
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TempSensADC1 ,
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TempSensADC2 ,
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TempSensADC3 ,
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TempSensADC4 ,
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TempSensADC5 ,
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TempSensADC6 ,
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TempSensADC7 ,
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TempSensDCDC ,
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VInSensDCDC ,
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VOutSensDCDC ,
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IOutSensDCDC ,
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FreqSensCore ,
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DutyCycleSensDCDC ,
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SpeedSensFan1 ,
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SpeedSensFan2 ,
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ErrorFlags ,
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BoardReady ,
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ClockSource ,
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IO_Level ,
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StartSource ,
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GlobalTriggerSource ,
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BusyInSource ,
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//EnableClockOutBackplane ,
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EnableClockOutFrontPanel ,
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TrgOutMode ,
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GPIOMode ,
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SyncOutMode ,
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BoardVetoSource ,
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BoardVetoWidth ,
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BoardVetoPolarity ,
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RunDelay ,
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EnableAutoDisarmACQ ,
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EnableDataReduction ,
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EnableStatisticEvents ,
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VolatileClockOutDelay ,
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PermanentClockOutDelay ,
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TestPulsePeriod ,
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TestPulseWidth ,
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TestPulseLowLevel ,
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TestPulseHighLevel ,
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ErrorFlagMask ,
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ErrorFlagDataMask ,
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DACoutMode ,
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DACoutStaticLevel ,
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DACoutChSelect ,
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EnableOffsetCalibration ,
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ITLAMainLogic ,
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ITLAMajorityLev ,
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ITLAPairLogic ,
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ITLAPolarity ,
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ITLAMask ,
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ITLAGateWidth ,
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ITLBMainLogic ,
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ITLBMajorityLev ,
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ITLBPairLogic ,
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ITLBPolarity ,
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ITLBMask ,
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ITLBGateWidth ,
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LVDSIOReg
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//LVDSTrgMask
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};
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}
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namespace VGA{
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const Reg VGAGain = PHA::VGA::VGAGain;
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}
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namespace LVDS{
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const Reg LVDSMode = PHA::LVDS::LVDSMode;
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const Reg LVDSDirection = PHA::LVDS::LVDSDirection;
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const std::vector<Reg> AllSettings = {
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LVDSMode ,
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LVDSDirection
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};
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}
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namespace CH{
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/// ========= red only
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const Reg SelfTrgRate = PHA::CH::SelfTrgRate;
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const Reg ChannelStatus = PHA::CH::ChannelStatus;
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const Reg GainFactor = PHA::CH::GainFactor;
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const Reg ADCToVolts = PHA::CH::ADCToVolts;
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const Reg ChannelRealtime = PHA::CH::ChannelRealtime;
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const Reg ChannelDeadtime = PHA::CH::ChannelDeadtime;
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const Reg ChannelTriggerCount = PHA::CH::ChannelTriggerCount;
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const Reg ChannelSavedCount = PHA::CH::ChannelSavedCount;
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const Reg ChannelWaveCount = PHA::CH::ChannelWaveCount;
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/// ======= read write
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const Reg ChannelEnable = PHA::CH::ChannelEnable;
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const Reg DC_Offset = PHA::CH::DC_Offset;
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const Reg TriggerThreshold = PHA::CH::TriggerThreshold;
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const Reg Polarity = PHA::CH::Polarity;
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const Reg WaveDataSource = PHA::CH::WaveDataSource;
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const Reg RecordLength = PHA::CH::RecordLength;
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const Reg PreTrigger = PHA::CH::PreTrigger;
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const Reg WaveSaving = PHA::CH::WaveSaving;
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const Reg WaveResolution = PHA::CH::WaveResolution;
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const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
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{"ADCInputBaseline", "ADC Input baseline"},
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{"CFDFilter", "CFD Filter"}});
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const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
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{"ADCInputBaseline", "ADC Input baseline"},
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{"CFDFilter", "CFD Filter"}});
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const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
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{"CFDFilterArmed", "CFD Filter Armed"},
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{"ReTriggerGuard", "ReTrigger Guard"},
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{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
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{"ADCInputOverthreshold", "ADC Input Over-threshold"},
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{"ChargeReady", "Charge Ready"},
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{"LongGate", "Long Gate"},
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{"ShortGate", "Short Gate"},
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{"PileUpTrigger", "Pile-up Trig."},
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{"ChargeOverRange", "Charge Over Range"},
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{"ADCSaturation", "ADC Saturate"},
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{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
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const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
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{"CFDFilterArmed", "CFD Filter Armed"},
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{"ReTriggerGuard", "ReTrigger Guard"},
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{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
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{"ADCInputOverthreshold", "ADC Input Over-threshold"},
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{"ChargeReady", "Charge Ready"},
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{"LongGate", "Long Gate"},
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{"ShortGate", "Short Gate"},
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{"PileUpTrigger", "Pile-up Trig."},
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{"ChargeOverRange", "Charge Over Range"},
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{"ADCSaturation", "ADC Saturate"},
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{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
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const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
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{"CFDFilterArmed", "CFD Filter Armed"},
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{"ReTriggerGuard", "ReTrigger Guard"},
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{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
|
||||
{"ADCInputOverthreshold", "ADC Input Over-threshold"},
|
||||
{"ChargeReady", "Charge Ready"},
|
||||
{"LongGate", "Long Gate"},
|
||||
{"ShortGate", "Short Gate"},
|
||||
{"PileUpTrigger", "Pile-up Trig."},
|
||||
{"ChargeOverRange", "Charge Over Range"},
|
||||
{"ADCSaturation", "ADC Saturate"},
|
||||
{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
|
||||
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
||||
{"CFDFilterArmed", "CFD Filter Armed"},
|
||||
{"ReTriggerGuard", "ReTrigger Guard"},
|
||||
{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
|
||||
{"ADCInputOverthreshold", "ADC Input Over-threshold"},
|
||||
{"ChargeReady", "Charge Ready"},
|
||||
{"LongGate", "Long Gate"},
|
||||
{"ShortGate", "Short Gate"},
|
||||
{"PileUpTrigger", "Pile-up Trig."},
|
||||
{"ChargeOverRange", "Charge Over Range"},
|
||||
{"ADCSaturation", "ADC Saturate"},
|
||||
{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
|
||||
|
||||
const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1};
|
||||
const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3};
|
||||
|
||||
|
||||
const Reg EventTriggerSource = PHA::CH::EventTriggerSource;
|
||||
const Reg ChannelsTriggerMask = PHA::CH::ChannelsTriggerMask;
|
||||
const Reg ChannelVetoSource = PHA::CH::ChannelVetoSource;
|
||||
const Reg WaveTriggerSource = PHA::CH::WaveTriggerSource;
|
||||
|
||||
const Reg EventSelector = PHA::CH::EventSelector;
|
||||
const Reg WaveSelector = PHA::CH::WaveSelector;
|
||||
const Reg CoincidenceMask = PHA::CH::CoincidenceMask;
|
||||
const Reg AntiCoincidenceMask = PHA::CH::AntiCoincidenceMask;
|
||||
const Reg CoincidenceLength = PHA::CH::CoincidenceLength;
|
||||
const Reg CoincidenceLengthSample = PHA::CH::CoincidenceLengthSample;
|
||||
|
||||
const Reg ADCVetoWidth = PHA::CH::ADCVetoWidth;
|
||||
|
||||
const Reg EventNeutronReject ("EventNeutronReject", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},{"Enabled", "Enabled"}});
|
||||
const Reg WaveNeutronReject ("WaveNeutronReject", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},{"Enabled", "Enabled"}});
|
||||
|
||||
const Reg EnergySkimLowDiscriminator = PHA::CH::EnergySkimLowDiscriminator;
|
||||
const Reg EnergySkimHighDiscriminator = PHA::CH::EnergySkimHighDiscriminator;
|
||||
|
||||
const Reg RecordLengthSample = PHA::CH::RecordLengthSample;
|
||||
const Reg PreTriggerSample = PHA::CH::PreTriggerSample;
|
||||
|
||||
const Reg ITLConnect = PHA::CH::ITLConnect;
|
||||
|
||||
const Reg ADCInputBaselineAvg ("ADCInputBaselineAvg", RW::ReadWrite, TYPE::CH, {{"Fixed", "Fixed"},
|
||||
{"Low", "Low"},
|
||||
{"MediumLow", "MediumLow"},
|
||||
{"MediumHigh", "MediumHigh"},
|
||||
{"High", "High"}});
|
||||
|
||||
const Reg AbsoluteBaseline ("AbsoluteBaseline", RW::ReadWrite, TYPE::CH, {{"0", ""},{"65535", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg ADCInputBaselineGuard ("ADCInputBaselineGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
|
||||
|
||||
const Reg SmoothingFactor ("SmoothingFactor", RW::ReadWrite, TYPE::CH, {{"1", "Disabled"},
|
||||
{"2", "Avg. 2 samples"},
|
||||
{"4", "Avg. 4 samples"},
|
||||
{"8", "Avg. 8 samples"},
|
||||
{"16", "Avg. 16 samples"}});
|
||||
|
||||
const Reg ChargeSmoothing ("ChargeSmoothing", RW::ReadWrite, TYPE::CH, {{"Enabled", "Enabled"}, {"Disabled", "Disabled"}});
|
||||
const Reg TimeFilterSmoothing ("TimeFilterSmoothing", RW::ReadWrite, TYPE::CH, {{"Enabled", "Enabled"}, {"Disabled", "Disabled"}});
|
||||
const Reg TriggerFilterSelection ("TriggerFilterSelection", RW::ReadWrite, TYPE::CH, {{"LeadingEdge", "Leading Edge"}, {"CFD", "CFD"}});
|
||||
|
||||
const Reg CFDDelay ("CFDDelayT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"8184", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
|
||||
const Reg CFDFraction ("CFDFraction", RW::ReadWrite, TYPE::CH, {{"25", ""},{"100", ""},{"0", ""}}, ANSTYPE::INTEGER, "%");
|
||||
|
||||
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
|
||||
|
||||
const Reg TriggerHysteresis ("TriggerHysteresis", RW::ReadWrite, TYPE::CH, {{"Enabled", "Enabled"}, {"Disabled", "Disabled"}});
|
||||
const Reg PileupGap ("PileupGap", RW::ReadWrite, TYPE::CH, {{"0", ""},{"65535", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg GateLongLength ("GateLongLengthT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"32000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
|
||||
const Reg GateShortLength ("GateShortLengthT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"32000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
|
||||
const Reg GateOffset ("GateOffsetT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"2000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
|
||||
const Reg LongChargeIntegratorPedestal ("LongChargeIntegratorPedestal", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "count");
|
||||
const Reg ShortChargeIntegratorPedestal ("ShortChargeIntegratorPedestal", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "count");
|
||||
|
||||
const Reg EnergyGain ("EnergyGain", RW::ReadWrite, TYPE::CH, {{"1", "No Gain"},
|
||||
{"4", "x4"},
|
||||
{"16", "x16"},
|
||||
{"64", "x64"},
|
||||
{"256", "x256"}});
|
||||
|
||||
const Reg NeutronThreshold ("NeutronThreshold", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "count");
|
||||
|
||||
const Reg ADCInputBaselineGuardSample ("ADCInputBaselineGuardS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg CFDDelaySample ("CFDDelayS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"1023", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg TimeFilterRetriggerGuardSample ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""},{"8", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg GateLongLengthSample ("GateLongLengthS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"4000", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg GateShortLengthSample ("GateShortLengthS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"4000", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
const Reg GateOffsetSample ("GateOffsetS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"250", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
|
||||
|
||||
|
||||
const std::vector<Reg> AllSettings = {
|
||||
SelfTrgRate ,
|
||||
ChannelStatus ,
|
||||
GainFactor ,
|
||||
ADCToVolts ,
|
||||
ChannelRealtime ,
|
||||
ChannelDeadtime ,
|
||||
ChannelTriggerCount ,
|
||||
ChannelSavedCount ,
|
||||
ChannelWaveCount ,
|
||||
ChannelEnable ,
|
||||
DC_Offset ,
|
||||
TriggerThreshold ,
|
||||
Polarity ,
|
||||
WaveDataSource ,
|
||||
RecordLength ,
|
||||
WaveSaving ,
|
||||
WaveResolution ,
|
||||
PreTrigger ,
|
||||
WaveAnalogProbe0 ,
|
||||
WaveAnalogProbe1 ,
|
||||
WaveDigitalProbe0 ,
|
||||
WaveDigitalProbe1 ,
|
||||
WaveDigitalProbe2 ,
|
||||
WaveDigitalProbe3 ,
|
||||
EventTriggerSource ,
|
||||
ChannelsTriggerMask ,
|
||||
ChannelVetoSource ,
|
||||
WaveTriggerSource ,
|
||||
EventSelector ,
|
||||
WaveSelector ,
|
||||
CoincidenceMask ,
|
||||
AntiCoincidenceMask ,
|
||||
CoincidenceLength ,
|
||||
CoincidenceLengthSample ,
|
||||
ADCVetoWidth ,
|
||||
EnergySkimLowDiscriminator ,
|
||||
EnergySkimHighDiscriminator,
|
||||
RecordLengthSample ,
|
||||
PreTriggerSample ,
|
||||
ITLConnect ,
|
||||
ADCInputBaselineAvg ,
|
||||
AbsoluteBaseline ,
|
||||
ADCInputBaselineGuard ,
|
||||
SmoothingFactor ,
|
||||
ChargeSmoothing ,
|
||||
TimeFilterSmoothing ,
|
||||
TriggerFilterSelection ,
|
||||
CFDDelay ,
|
||||
CFDFraction ,
|
||||
TimeFilterRetriggerGuard ,
|
||||
TriggerHysteresis ,
|
||||
PileupGap ,
|
||||
GateLongLength ,
|
||||
GateShortLength ,
|
||||
GateOffset ,
|
||||
LongChargeIntegratorPedestal,
|
||||
ShortChargeIntegratorPedestal,
|
||||
EnergyGain ,
|
||||
NeutronThreshold ,
|
||||
ADCInputBaselineGuardSample,
|
||||
CFDDelaySample ,
|
||||
TimeFilterRetriggerGuardSample,
|
||||
GateLongLengthSample ,
|
||||
GateShortLengthSample ,
|
||||
GateOffsetSample
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -430,6 +430,20 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
|
|||
cbbBdVetoPolarity[iDigi] = new RComboBox(tab);
|
||||
boardLayout->addWidget(cbbBdVetoPolarity[iDigi], rowId, 6);
|
||||
SetupShortComboBox(cbbBdVetoPolarity[iDigi], PHA::DIG::BoardVetoPolarity);
|
||||
connect(cbbBdVetoPolarity[iDigi], &RComboBox::currentIndexChanged, this, [=](){
|
||||
if( !enableSignalSlot ) return;
|
||||
QString msg;
|
||||
msg = "DIG:"+ QString::number(digi[ID]->GetSerialNumber()) + "|" + QString::fromStdString(PHA::DIG::BoardVetoPolarity.GetPara());
|
||||
msg += " = " + cbbBdVetoPolarity[ID]->currentData().toString();
|
||||
if( digi[ID]->WriteValue(PHA::DIG::BoardVetoPolarity, cbbStatEvents[ID]->currentData().toString().toStdString()) ){
|
||||
SendLogMsg(msg + "|OK.");
|
||||
cbbBdVetoPolarity[ID]->setStyleSheet("");
|
||||
}else{
|
||||
SendLogMsg(msg + "|Fail.");
|
||||
cbbBdVetoPolarity[ID]->setStyleSheet("color:red");
|
||||
}
|
||||
});
|
||||
|
||||
|
||||
//-------------------------------------
|
||||
rowId ++;
|
||||
|
|
@ -1966,7 +1980,7 @@ void DigiSettingsPanel::LoadSettings(){
|
|||
|
||||
void DigiSettingsPanel::SetDefaultPHASettigns(){
|
||||
SendLogMsg("Program Digitizer-" + QString::number(digi[ID]->GetSerialNumber()) + " to default PHA.");
|
||||
digi[ID]->ProgramPHABoard();
|
||||
digi[ID]->ProgramDPPBoard();
|
||||
digi[ID]->ProgramPHAChannels();
|
||||
RefreshSettings();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -696,7 +696,7 @@ void MainWindow::OpenDigitizers(){
|
|||
digi[i]->SetSettingFileName("");
|
||||
//LogMsg("Reset digitizer And set default PHA settings.");
|
||||
//digi[i]->Reset();
|
||||
//digi[i]->ProgramPHABoard(false);
|
||||
//digi[i]->ProgramDPPBoard(false);
|
||||
}
|
||||
|
||||
digi[i]->ReadAllSettings();
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user