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add more data in Reg class

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This commit is contained in:
Ryan Tang 2023-02-24 19:21:27 -05:00
parent f6f4d1b96d
commit 7be2aea72a
4 changed files with 375 additions and 142 deletions
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26
ClassDigitizer2Gen.h
View File

@ -135,7 +135,7 @@ class Digitizer2Gen {
void ReadAllSettings(); // read settings from digitier and save to memory void ReadAllSettings(); // read settings from digitier and save to memory
bool SaveSettingsToFile(const char * saveFileName = NULL); // ReadAllSettings + text file bool SaveSettingsToFile(const char * saveFileName = NULL); // ReadAllSettings + text file
bool LoadSettingsFromFile(const char * loadFileName = NULL); // Load settings, write to digitizer and save to memory bool LoadSettingsFromFile(const char * loadFileName = NULL); // Load settings, write to digitizer and save to memory
std::string GetSettingValue(TYPE type, unsigned short index, int ch_index = -1) const { std::string GetSettingValue(TYPE type, unsigned short index, unsigned int ch_index = 0) const {
switch(type){ switch(type){
case TYPE::DIG: return boardSettings[index].GetValue(); case TYPE::DIG: return boardSettings[index].GetValue();
case TYPE::CH: return chSettings[ch_index][index].GetValue(); case TYPE::CH: return chSettings[ch_index][index].GetValue();
@ -144,6 +144,30 @@ class Digitizer2Gen {
} }
return "invalid"; return "invalid";
} }
std::string GetSettingValue(TYPE type, const Reg para, unsigned int ch_index = 0) const{
switch(type){
case TYPE::DIG:{
for( int i = 0; i < (int) boardSettings.size(); i++){
if( para.GetPara() == boardSettings[i].GetPara()){
return boardSettings[i].GetValue();
}
}
};break;
case TYPE::CH:{
for( int i = 0; i < (int) chSettings[ch_index].size(); i++){
if( para.GetPara() == chSettings[ch_index][i].GetPara()){
return chSettings[ch_index][i].GetValue();
}
}
};break;
case TYPE::VGA: return VGASetting[ch_index].GetValue();
case TYPE::LVDS: return "not defined";
default : return "invalid";
}
return "no such parameter";
}
}; };
#endif #endif

417
DigiParameters.h
View File

@ -5,6 +5,7 @@
#include <string> #include <string>
#include <vector> #include <vector>
enum ANSTYPE {NUM, STR, NONE};
enum TYPE {CH, DIG, LVDS, VGA}; enum TYPE {CH, DIG, LVDS, VGA};
enum RW { ReadOnly, WriteOnly, ReadWrite}; enum RW { ReadOnly, WriteOnly, ReadWrite};
@ -16,26 +17,45 @@ class Reg {
TYPE type; TYPE type;
RW readWrite; // true for read/write, false for read-only RW readWrite; // true for read/write, false for read-only
bool isCmd; bool isCmd;
ANSTYPE ansType;
std::string answerUnit;
std::vector<std::pair<std::string, std::string>> answer;
public: public:
Reg(){ Reg(){
this->name = ""; name = "";
this->readWrite = RW::ReadWrite; readWrite = RW::ReadWrite;
this->type = TYPE::CH; type = TYPE::CH;
this->isCmd = false; isCmd = false;
this->value = ""; value = "";
ansType = ANSTYPE::STR;
answerUnit = "";
answer.clear();
} }
Reg(std::string para, RW readwrite, TYPE type = TYPE::CH, bool isCmd = false){ Reg(std::string para, RW readwrite,
TYPE type = TYPE::CH,
std::vector<std::pair<std::string,std::string>> answer = {},
ANSTYPE ansType = ANSTYPE::STR,
std::string ansUnit = "",
bool isCmd = false){
this->name = para; this->name = para;
this->readWrite = readwrite; this->readWrite = readwrite;
this->type = type; this->type = type;
this->isCmd = isCmd; this->isCmd = isCmd;
this->value = ""; this->value = "";
this->ansType = ansType;
this->answer = answer;
this->answerUnit = ansUnit;
} }
~Reg(){}; ~Reg(){};
void SetValue(std::string sv) { this->value = sv;} void SetValue(std::string sv) { this->value = sv;}
std::string GetValue() const { return value;} std::string GetValue() const { return value;}
RW ReadWrite() const {return readWrite;}
TYPE GetType() const {return type;}
ANSTYPE GetAnswerType() const {return ansType;}
std::string GetUnit() const {return answerUnit;}
std::vector<std::pair<std::string,std::string>> GetAnswers() const {return answer;}
std::string GetPara() const {return name;} std::string GetPara() const {return name;}
std::string GetFullPara(int ch_index = -1) const { std::string GetFullPara(int ch_index = -1) const {
@ -76,8 +96,7 @@ class Reg {
return "invalid"; break; return "invalid"; break;
} }
} }
RW ReadWrite() const {return readWrite;}
TYPE GetType() const {return type;}
operator std::string () const {return name;} // this allow Reg kaka("XYZ", true); std::string haha = kaka; operator std::string () const {return name;} // this allow Reg kaka("XYZ", true); std::string haha = kaka;
@ -97,100 +116,152 @@ namespace DIGIPARA{
///============== read only ///============== read only
const Reg CupVer ("CupVer", RW::ReadOnly, TYPE::DIG); const Reg CupVer ("CupVer", RW::ReadOnly, TYPE::DIG);
const Reg FPGA_firmwareVersion ("FPGA_FwVer", RW::ReadOnly, TYPE::DIG); const Reg FPGA_firmwareVersion ("FPGA_FwVer", RW::ReadOnly, TYPE::DIG);
const Reg FirmwareType ("FwType", RW::ReadOnly, TYPE::DIG); const Reg FirmwareType ("FwType", RW::ReadOnly, TYPE::DIG, {{"DPP_PHA", ""}, {"DPP_ZLE", ""}, {"DPP_PSD", ""}, {"DPP_DAW", ""}, {"DPP_OPEN", ""}, {"Scope", ""}});
const Reg ModelCode ("ModelCode", RW::ReadOnly, TYPE::DIG); const Reg ModelCode ("ModelCode", RW::ReadOnly, TYPE::DIG);
const Reg PBCode ("PBCode", RW::ReadOnly, TYPE::DIG); const Reg PBCode ("PBCode", RW::ReadOnly, TYPE::DIG);
const Reg ModelName ("ModelName", RW::ReadOnly, TYPE::DIG); const Reg ModelName ("ModelName", RW::ReadOnly, TYPE::DIG);
const Reg FromFactor ("FormFactor", RW::ReadOnly, TYPE::DIG); const Reg FromFactor ("FormFactor", RW::ReadOnly, TYPE::DIG, {{"0", "VME"}, {"1", "VME64X"}, {"2", "DT"}});
const Reg FamilyCode ("FamilyCode", RW::ReadOnly, TYPE::DIG); const Reg FamilyCode ("FamilyCode", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
const Reg SerialNumber ("SerialNum", RW::ReadOnly, TYPE::DIG); const Reg SerialNumber ("SerialNum", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
const Reg PCBrev_MB ("PCBrev_MB", RW::ReadOnly, TYPE::DIG); const Reg PCBrev_MB ("PCBrev_MB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
const Reg PCBrev_PB ("PCBrev_PB", RW::ReadOnly, TYPE::DIG); const Reg PCBrev_PB ("PCBrev_PB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
const Reg DPP_License ("License", RW::ReadOnly, TYPE::DIG); const Reg DPP_License ("License", RW::ReadOnly, TYPE::DIG);
const Reg DPP_LicenseStatus ("LicenseStatus", RW::ReadOnly, TYPE::DIG); const Reg DPP_LicenseStatus ("LicenseStatus", RW::ReadOnly, TYPE::DIG);
const Reg DPP_LicenseRemainingTime ("LicenseRemainingTime", RW::ReadOnly, TYPE::DIG); const Reg DPP_LicenseRemainingTime ("LicenseRemainingTime", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
const Reg NumberOfChannel ("NumCh", RW::ReadOnly, TYPE::DIG); const Reg NumberOfChannel ("NumCh", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "sec");
const Reg ADC_bit ("ADC_Nbit", RW::ReadOnly, TYPE::DIG); const Reg ADC_bit ("ADC_Nbit", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
const Reg ADC_SampleRate ("ADC_SamplRate", RW::ReadOnly, TYPE::DIG); const Reg ADC_SampleRate ("ADC_SamplRate", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "MS/s");
const Reg InputDynamicRange ("InputRange", RW::ReadOnly, TYPE::DIG); const Reg InputDynamicRange ("InputRange", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Vpp");
const Reg InputType ("InputType", RW::ReadOnly, TYPE::DIG); const Reg InputType ("InputType", RW::ReadOnly, TYPE::DIG, {{"0","Singled ended"}, {"1", "Differential"}});
const Reg InputImpedance ("Zin", RW::ReadOnly, TYPE::DIG); const Reg InputImpedance ("Zin", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Ohm");
const Reg IPAddress ("IPAddress", RW::ReadOnly, TYPE::DIG); const Reg IPAddress ("IPAddress", RW::ReadOnly, TYPE::DIG);
const Reg NetMask ("Netmask", RW::ReadOnly, TYPE::DIG); const Reg NetMask ("Netmask", RW::ReadOnly, TYPE::DIG);
const Reg Gateway ("Gateway", RW::ReadOnly, TYPE::DIG); const Reg Gateway ("Gateway", RW::ReadOnly, TYPE::DIG);
const Reg LED_status ("LedStatus", RW::ReadOnly, TYPE::DIG); const Reg LED_status ("LedStatus", RW::ReadOnly, TYPE::DIG);
const Reg ACQ_status ("AcquisitionStatus", RW::ReadOnly, TYPE::DIG); const Reg ACQ_status ("AcquisitionStatus", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "byte");
const Reg MaxRawDataSize ("MaxRawDataSize", RW::ReadOnly, TYPE::DIG); const Reg MaxRawDataSize ("MaxRawDataSize", RW::ReadOnly, TYPE::DIG);
const Reg TempSensAirIn ("TempSensAirIn", RW::ReadOnly, TYPE::DIG); const Reg TempSensAirIn ("TempSensAirIn", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensAirOut ("TempSensAirOut", RW::ReadOnly, TYPE::DIG); const Reg TempSensAirOut ("TempSensAirOut", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensCore ("TempSensCore", RW::ReadOnly, TYPE::DIG); const Reg TempSensCore ("TempSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensFirstADC ("TempSensFirstADC", RW::ReadOnly, TYPE::DIG); const Reg TempSensFirstADC ("TempSensFirstADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensLastADC ("TempSensLastADC", RW::ReadOnly, TYPE::DIG); const Reg TempSensLastADC ("TempSensLastADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensHottestADC ("TempSensHottestADC", RW::ReadOnly, TYPE::DIG); const Reg TempSensHottestADC ("TempSensHottestADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC0 ("TempSensADC0", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC0 ("TempSensADC0", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC1 ("TempSensADC1", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC1 ("TempSensADC1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC2 ("TempSensADC2", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC2 ("TempSensADC2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC3 ("TempSensADC3", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC3 ("TempSensADC3", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC4 ("TempSensADC4", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC4 ("TempSensADC4", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC5 ("TempSensADC5", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC5 ("TempSensADC5", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC6 ("TempSensADC6", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC6 ("TempSensADC6", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg TempSensADC7 ("TempSensADC7", RW::ReadOnly, TYPE::DIG); const Reg TempSensADC7 ("TempSensADC7", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7}; const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7};
const Reg TempSensDCDC ("TempSensDCDC", RW::ReadOnly, TYPE::DIG); const Reg TempSensDCDC ("TempSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
const Reg VInSensDCDC ("VInSensDCDC", RW::ReadOnly, TYPE::DIG); const Reg VInSensDCDC ("VInSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "V");
const Reg VOutSensDCDC ("VOutSensDCDC", RW::ReadOnly, TYPE::DIG); const Reg VOutSensDCDC ("VOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "V");
const Reg IOutSensDCDC ("IOutSensDCDC", RW::ReadOnly, TYPE::DIG); const Reg IOutSensDCDC ("IOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Amp");
const Reg FreqSensCore ("FreqSensCore", RW::ReadOnly, TYPE::DIG); const Reg FreqSensCore ("FreqSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Hz");
const Reg DutyCycleSensDCDC ("DutyCycleSensDCDC", RW::ReadOnly, TYPE::DIG); const Reg DutyCycleSensDCDC ("DutyCycleSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "%");
const Reg SpeedSensFan1 ("SpeedSensFan1", RW::ReadOnly, TYPE::DIG); const Reg SpeedSensFan1 ("SpeedSensFan1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "rpm");
const Reg SpeedSensFan2 ("SpeedSensFan2", RW::ReadOnly, TYPE::DIG); const Reg SpeedSensFan2 ("SpeedSensFan2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "rpm");
const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG); const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG);
const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG); const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG, {{"True", "No Error"}, {"False", "Error"}});
///============= read write ///============= read write
const Reg ClockSource ("ClockSource", RW::ReadWrite, TYPE::DIG); const Reg ClockSource ("ClockSource", RW::ReadWrite, TYPE::DIG, {{"Internal", "Internal Clock 62.5 MHz"},
const Reg IO_Level ("IOlevel", RW::ReadWrite, TYPE::DIG); {"FPClkIn", "Front Plane Clock Input"}});
const Reg StartSource ("StartSource", RW::ReadWrite, TYPE::DIG); const Reg IO_Level ("IOlevel", RW::ReadWrite, TYPE::DIG, {{"NIM", "NIM (0=0V, 1=-0.8V) "}, {"TTL", "TTL (0=0V, 1=3.3V)"}});
const Reg GlobalTriggerSource ("GlobalTriggerSource", RW::ReadWrite, TYPE::DIG); const Reg StartSource ("StartSource", RW::ReadWrite, TYPE::DIG, {{"EncodedClkIn", "font panel CLK-IN/SYNC"},
{"SINlevel", "S-IN Level"},
{"SINedge", "S-IN Edge"},
{"SWcmd", "Software"},
{"LVDS", "LVDS"},
{"PO", "Backplane"}});
const Reg GlobalTriggerSource ("GlobalTriggerSource", RW::ReadWrite, TYPE::DIG,{{"TrgIn", "TRG-IN" },
{"P0", "Back Plane" },
{"SwTrg", "Software Trigger" },
{"GPIO", "GPIO" },
{"TestPulse", "Test Pulse" },
{"LVDS", "LVDS"}});
const Reg BusyInSource ("BusyInSource", RW::ReadWrite, TYPE::DIG); const Reg BusyInSource ("BusyInSource", RW::ReadWrite, TYPE::DIG, {{"SIN", "SIN"},
{"GPIO", "GPIO"},
{"LVDS", "LVDS"},
{"Disabled","Disabled"}});
//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG); //const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
const Reg EnableClockOutFrontPanel ("EnClockOutFP", RW::ReadWrite, TYPE::DIG); const Reg EnableClockOutFrontPanel ("EnClockOutFP", RW::ReadWrite, TYPE::DIG, {{"True", "Enable"}, {"False", "Disabled"}});
const Reg TrgOutMode ("TrgOutMode", RW::ReadWrite, TYPE::DIG); const Reg TrgOutMode ("TrgOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
const Reg GPIOMode ("GPIOMode", RW::ReadWrite, TYPE::DIG); {"TRGIN", "TRG-IN"},
const Reg SyncOutMode ("SyncOutMode", RW::ReadWrite, TYPE::DIG); {"SwTrg", "Software Trigger"},
{"LVDS", "LVDS"},
const Reg BoardVetoSource ("BoardVetoSource", RW::ReadWrite, TYPE::DIG); {"Run", "Run Signal"},
const Reg BoardVetoWidth ("BoardVetoWidth", RW::ReadWrite, TYPE::DIG); {"RefClk", "Reference Clock"},
const Reg BoardVetoPolarity ("BoardVetoPolarity", RW::ReadWrite, TYPE::DIG); {"TestPulse", "Test Pulse"},
const Reg RunDelay ("RunDelay", RW::ReadWrite, TYPE::DIG); {"Busy", "Busy Signal"},
const Reg EnableAutoDisarmACQ ("EnAutoDisarmAcq", RW::ReadWrite, TYPE::DIG); {"Fixed0", "0-level"},
const Reg EnableDataReduction ("EnDataReduction", RW::ReadWrite, TYPE::DIG); {"Fixed1", "1-level"},
const Reg EnableStatisticEvents ("EnStatEvents", RW::ReadWrite, TYPE::DIG); {"SyncIn", "SyncIn Signal"},
const Reg VolatileClockOutDelay ("VolatileClockOutDelay", RW::ReadWrite, TYPE::DIG); {"SIN", "S-IN Signal"},
const Reg PermanentClockOutDelay ("PermanentClockOutDelay", RW::ReadWrite, TYPE::DIG); {"GPIO", "GPIO Signal"},
const Reg TestPulsePeriod ("TestPulsePeriod", RW::ReadWrite, TYPE::DIG); {"AccepTrg", "Acceped Trigger Signal"},
const Reg TestPulseWidth ("TestPulseWidth", RW::ReadWrite, TYPE::DIG); {"TrgClk", "Trigger Clock"}});
const Reg TestPulseLowLevel ("TestPulseLowLevel", RW::ReadWrite, TYPE::DIG); const Reg GPIOMode ("GPIOMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
const Reg TestPulseHighLevel ("TestPulseHighLevel", RW::ReadWrite, TYPE::DIG); {"TRGIN", "TRG-IN"},
{"P0", "Back Plane"},
{"SIN", "S-IN Signal"},
{"LVDS", "LVDS Trigger"},
{"SwTrg", "Software Trigger"},
{"Run", "Run Signal"},
{"RefClk", "Referece Clock"},
{"TestPulse", "Test Pulse"},
{"Busy", "Busy Signal"},
{"Fixed0", "0-Level"},
{"Fixed1", "1-Level"}});
const Reg SyncOutMode ("SyncOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
{"SyncIn", "Sync-In Signal"},
{"TestPulse", "Test Pulse"},
{"IntClk", "Internal Clock 62.5MHz"},
{"Run", "Run Signal"} });
const Reg BoardVetoSource ("BoardVetoSource", RW::ReadWrite, TYPE::DIG, {{"SIN", "S-IN"},
{"LVDS", "LVDS"},
{"GPIO", "GPIO"},
{"P0", "Back Plane"},
{"Disabled", "Disabled"} });
const Reg BoardVetoWidth ("BoardVetoWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"34359738360", ""}}, ANSTYPE::NUM, "ns");
const Reg BoardVetoPolarity ("BoardVetoPolarity", RW::ReadWrite, TYPE::DIG, {{"ActiveHigh", "Active when high"}, {"ActiveLow", "Active when low"}});
const Reg RunDelay ("RunDelay", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"524280", ""}}, ANSTYPE::NUM, "ns");
const Reg EnableAutoDisarmACQ ("EnAutoDisarmAcq", RW::ReadWrite, TYPE::DIG, {{"True", "Auto disarmed"}, {"False", "Disabled"}});
const Reg EnableDataReduction ("EnDataReduction", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
const Reg EnableStatisticEvents ("EnStatEvents", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
const Reg VolatileClockOutDelay ("VolatileClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}}, ANSTYPE::NUM, "ps");
const Reg PermanentClockOutDelay ("PermanentClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}}, ANSTYPE::NUM, "ps");
const Reg TestPulsePeriod ("TestPulsePeriod", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}}, ANSTYPE::NUM, "ns");
const Reg TestPulseWidth ("TestPulseWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}}, ANSTYPE::NUM, "ns");
const Reg TestPulseLowLevel ("TestPulseLowLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}}, ANSTYPE::NUM, "ns");
const Reg TestPulseHighLevel ("TestPulseHighLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}}, ANSTYPE::NUM, "ns");
const Reg ErrorFlagMask ("ErrorFlagMask", RW::ReadWrite, TYPE::DIG); const Reg ErrorFlagMask ("ErrorFlagMask", RW::ReadWrite, TYPE::DIG);
const Reg ErrorFlagDataMask ("ErrorFlagDataMask", RW::ReadWrite, TYPE::DIG); const Reg ErrorFlagDataMask ("ErrorFlagDataMask", RW::ReadWrite, TYPE::DIG);
const Reg DACoutMode ("DACoutMode", RW::ReadWrite, TYPE::DIG); const Reg DACoutMode ("DACoutMode", RW::ReadWrite, TYPE::DIG, {{"Static", "DAC fixed level"},
const Reg DACoutStaticLevel ("DACoutStaticLevel", RW::ReadWrite, TYPE::DIG); {"ChInput", "From Channel"},
const Reg DACoutChSelect ("DACoutChSelect", RW::ReadWrite, TYPE::DIG); {"ChSum", "Sum of all Channels"},
const Reg EnableOffsetCalibration ("EnOffsetCalibration", RW::ReadWrite, TYPE::DIG); {"OverThrSum", "Number of Channels triggered"},
{"Ramp", "14-bit counter"},
{"Sin5MHz", "5 MHz Sin wave"},
{"Square", "Test Pulse"}});
const Reg DACoutStaticLevel ("DACoutStaticLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"16383", ""}}, ANSTYPE::NUM, "units");
const Reg DACoutChSelect ("DACoutChSelect", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"64", ""}}, ANSTYPE::NUM);
const Reg EnableOffsetCalibration ("EnOffsetCalibration", RW::ReadWrite, TYPE::DIG, {{"True", "Applied Cali."}, {"False", "No Cali."}});
/// ========== command /// ========== command
const Reg Reset ("Reset", RW::WriteOnly, TYPE::DIG, true); const Reg Reset ("Reset", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const Reg ClearData ("ClearData", RW::WriteOnly, TYPE::DIG, true); // clear memory, setting not affected const Reg ClearData ("ClearData", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // clear memory, setting not affected
const Reg ArmACQ ("ArmAcquisition", RW::WriteOnly, TYPE::DIG, true); const Reg ArmACQ ("ArmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const Reg DisarmACQ ("DisarmAcquisition", RW::WriteOnly, TYPE::DIG, true); const Reg DisarmACQ ("DisarmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const Reg SoftwareStartACQ ("SwStartAcquisition", RW::WriteOnly, TYPE::DIG, true); // only when SwStart in StartSource const Reg SoftwareStartACQ ("SwStartAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only when SwStart in StartSource
const Reg SoftwareStopACQ ("SwStopAcquisition", RW::WriteOnly, TYPE::DIG, true); // stop ACQ, whatever start source const Reg SoftwareStopACQ ("SwStopAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // stop ACQ, whatever start source
const Reg SendSoftwareTrigger ("SendSWTrigger", RW::WriteOnly, TYPE::DIG, true); // only work when Swtrg in the GlobalTriggerSource const Reg SendSoftwareTrigger ("SendSWTrigger", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only work when Swtrg in the GlobalTriggerSource
const Reg ReloadCalibration ("ReloadCalibration", RW::WriteOnly, TYPE::DIG, true); const Reg ReloadCalibration ("ReloadCalibration", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const std::vector<Reg> AllSettings = { const std::vector<Reg> AllSettings = {
@ -279,13 +350,13 @@ namespace DIGIPARA{
} }
namespace VGA{ namespace VGA{
const Reg VGAGain ("VGAGain", RW::ReadWrite, TYPE::VGA); // VX2745 only const Reg VGAGain ("VGAGain", RW::ReadWrite, TYPE::VGA, {{"0", ""},{"40", ""}}, ANSTYPE::NUM, "dB"); // VX2745 only
} }
namespace CH{ namespace CH{
/// ========= red only /// ========= red only
const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly); const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::NUM, "Hz");
const Reg ChannelStatus ("ChStatus", RW::ReadOnly); const Reg ChannelStatus ("ChStatus", RW::ReadOnly);
const Reg GainFactor ("GainFactor", RW::ReadOnly); const Reg GainFactor ("GainFactor", RW::ReadOnly);
const Reg ADCToVolts ("ADCToVolts", RW::ReadOnly); const Reg ADCToVolts ("ADCToVolts", RW::ReadOnly);
@ -297,53 +368,157 @@ namespace DIGIPARA{
const Reg ChannelWaveCount ("ChWaveCnt", RW::ReadOnly); const Reg ChannelWaveCount ("ChWaveCnt", RW::ReadOnly);
/// ======= read write /// ======= read write
const Reg ChannelEnable ("ChEnable", RW::ReadWrite); const Reg ChannelEnable ("ChEnable", RW::ReadWrite, TYPE::CH, {{"True", "Enabled"}, {"False", "Disabled"}});
const Reg DC_Offset ("DCOffset", RW::ReadWrite); const Reg DC_Offset ("DCOffset", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"100", ""}}, ANSTYPE::NUM, "%");
const Reg TriggerThreshold ("TriggerThr", RW::ReadWrite); const Reg TriggerThreshold ("TriggerThr", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8191", ""}}, ANSTYPE::NUM);
const Reg Polarity ("PulsePolarity", RW::ReadWrite); const Reg Polarity ("PulsePolarity", RW::ReadWrite, TYPE::CH, {{"Positive", "Pos. +"},{"Negative", "Neg. -"}});
const Reg WaveDataSource ("WaveDataSource", RW::ReadWrite); const Reg WaveDataSource ("WaveDataSource", RW::ReadWrite, TYPE::CH, {{"ADC_DATA", "Input ADC"},
const Reg RecordLength ("ChRecordLengthT", RW::ReadWrite); {"ADC_TEST_TOGGLE", "ADC produces TOGGLE signal"},
const Reg PreTrigger ("ChPreTriggerT", RW::ReadWrite); {"ADC_TEST_RAMP", "ADC produces RAMP signal"},
const Reg WaveSaving ("WaveSaving", RW::ReadWrite); {"ADC_TEST_SIN", "ADC produce SIN signal"},
const Reg WaveResolution ("WaveResolution", RW::ReadWrite); {"Ramp", "Ramp generator"},
const Reg TimeFilterRiseTime ("TimeFilterRiseTimeT", RW::ReadWrite); {"SquareWave", "Test Pusle (Square Wave)"} });
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite); const Reg RecordLength ("ChRecordLengthT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"64800", ""}}, ANSTYPE::NUM, "ns");
const Reg EnergyFilterRiseTime ("EnergyFilterRiseTimeT", RW::ReadWrite); const Reg PreTrigger ("ChPreTriggerT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"32000", ""}}, ANSTYPE::NUM, "ns");
const Reg EnergyFilterFlatTop ("EnergyFilterFlatTopT", RW::ReadWrite); const Reg WaveSaving ("WaveSaving", RW::ReadWrite, TYPE::CH, {{"Always", "Always"}, {"OnRequest", "On Request"}});
const Reg EnergyFilterPoleZero ("EnergyFilterPoleZeroT", RW::ReadWrite); const Reg WaveResolution ("WaveResolution", RW::ReadWrite, TYPE::CH, {{"Res8", " 8 ns"},
const Reg EnergyFilterPeakingPosition ("EnergyFilterPeakingPosition", RW::ReadWrite); {"Res16","16 ns"},
const Reg EnergyFilterPeakingAvg ("EnergyFilterPeakingAvg", RW::ReadWrite); {"Res32","32 ns"},
const Reg EnergyFilterBaselineAvg ("EnergyFilterBaselineAvg", RW::ReadWrite); {"Res64","64 ns"}});
const Reg EnergyFilterBaselineGuard ("EnergyFilterBaselineGuardT", RW::ReadWrite); const Reg TimeFilterRiseTime ("TimeFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"2000", ""}}, ANSTYPE::NUM, "ns");
const Reg EnergyFilterFineGain ("EnergyFilterFineGain", RW::ReadWrite); const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}}, ANSTYPE::NUM, "ns");
const Reg EnergyFilterPileUpGuard ("EnergyFilterPileUpGuardT", RW::ReadWrite); const Reg EnergyFilterRiseTime ("EnergyFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"13000", ""}}, ANSTYPE::NUM, "ns");
const Reg EnergyFilterLowFreqFilter ("EnergyFilterLFLimitation", RW::ReadWrite); const Reg EnergyFilterFlatTop ("EnergyFilterFlatTopT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"3000", ""}}, ANSTYPE::NUM, "ns");
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite); const Reg EnergyFilterPoleZero ("EnergyFilterPoleZeroT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"524000", ""}}, ANSTYPE::NUM, "ns");
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite); const Reg EnergyFilterPeakingPosition ("EnergyFilterPeakingPosition", RW::ReadWrite, TYPE::CH, {{"0", ""},{"100", ""}}, ANSTYPE::NUM, "%");
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite); const Reg EnergyFilterPeakingAvg ("EnergyFilterPeakingAvg", RW::ReadWrite, TYPE::CH, {{"OneShot", " 1 sample"},
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite); {"LowAVG", " 4 samples"},
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite); {"MediumAVG", "16 samples"},
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite); {"HighAVG", "64 samples"}});
const Reg EnergyFilterBaselineAvg ("EnergyFilterBaselineAvg", RW::ReadWrite, TYPE::CH, {{"Fixed", " 0 sample"},
{"VeryLow", " 16 samples"},
{"Low", " 64 samples"},
{"MediumLow", " 256 samples"},
{"Medium", " 1024 samples"},
{"MediumHigh"," 4096 samples"},
{"High", "16384 samples"}});
const Reg EnergyFilterBaselineGuard ("EnergyFilterBaselineGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}}, ANSTYPE::NUM, "ns");
const Reg EnergyFilterFineGain ("EnergyFilterFineGain", RW::ReadWrite, TYPE::CH, {{"0", ""},{"10", ""}}, ANSTYPE::NUM);
const Reg EnergyFilterPileUpGuard ("EnergyFilterPileUpGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"64000", ""}}, ANSTYPE::NUM);
const Reg EnergyFilterLowFreqFilter ("EnergyFilterLFLimitation", RW::ReadWrite, TYPE::CH, {{"0", "Disabled"}, {"1", "Enabled"}});
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
{"TimeFilter", "Time Filter"},
{"EnergyFilter", "Trapazoid"},
{"EnergyFilterBase", "Trap. Baseline"},
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
{"TimeFilter", "Time Filter"},
{"EnergyFilter", "Trapazoid"},
{"EnergyFilterBase", "Trap. Baseline"},
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1}; const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1};
const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3}; const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3};
const Reg EventTriggerSource ("EventTriggerSource", RW::ReadWrite);
const Reg ChannelsTriggerMask ("ChannelsTriggerMask", RW::ReadWrite); const Reg EventTriggerSource ("EventTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
const Reg ChannelVetoSource ("ChannelVetoSource", RW::ReadWrite); {"TRGIN", "TRG-IN"},
const Reg WaveTriggerSource ("WaveTriggerSource", RW::ReadWrite); {"SWTrigger", "Software Trigger"},
const Reg EventSelector ("EventSelector", RW::ReadWrite); {"ChSelfTrigger", "Channel Self-Trigger"},
const Reg WaveSelector ("WaveSelector", RW::ReadWrite); {"Ch64Trigger", "Channel 64-Trigger"},
const Reg CoincidenceMask ("CoincidenceMask", RW::ReadWrite); {"Disabled", "Disabled"}});
const Reg AntiCoincidenceMask ("AntiCoincidenceMask", RW::ReadWrite); const Reg ChannelsTriggerMask ("ChannelsTriggerMask", RW::ReadWrite, TYPE::CH, {}, ANSTYPE::STR, "64-bit" );
const Reg CoincidenceLength ("CoincidenceLengthT", RW::ReadWrite); const Reg ChannelVetoSource ("ChannelVetoSource", RW::ReadWrite, TYPE::CH, {{"BoardVeto", "Board Veto"},
{"ADCOverSaturation", "ADC Over Saturation"},
{"ADCUnderSaturation", "ADC Under Saturation"}});
const Reg WaveTriggerSource ("WaveTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
{"TRGIN", "TRG-IN"},
{"ExternalInhibit", "External Inhibit"},
{"ADCUnderSaturation", "ADC Under Saturation"},
{"ADCOverSaturation", "ADC Over Saturation"},
{"SWTrigger", "Software Trigger"},
{"ChSelfTrigger", "Channel Self-Trigger"},
{"Ch64Trigger", "Channel 64-Trigger"},
{"Disabled", "Disabled"}});
const Reg EventSelector ("EventSelector", RW::ReadWrite, TYPE::CH, {{"All", "All"},
{"Pileup", "Pile up"},
{"EnergySkim", "Energy Skim"}});
const Reg WaveSelector ("WaveSelector", RW::ReadWrite, TYPE::CH, {{"All", "All wave"},
{"Pileup", "Only Pile up"},
{"EnergySkim", "Only in Energy Skim Range"}});
const Reg CoincidenceMask ("CoincidenceMask", RW::ReadWrite, TYPE::CH, {{"Disable", "Disabled"},
{"Ch64Trigger", "Channel 64-Trigger"},
{"TRGIN", "TRG-IN"},
{"GlobalTriggerSource", "Global Trigger"},
{"ITLA", "ITLA"},
{"ITLB", "ITLB"}});
const Reg AntiCoincidenceMask ("AntiCoincidenceMask", RW::ReadWrite, TYPE::CH,{{"Disable", "Disabled"},
{"Ch64Trigger", "Channel 64-Trigger"},
{"TRGIN", "TRG-IN"},
{"GlobalTriggerSource", "Global Trigger"},
{"ITLA", "ITLA"},
{"ITLB", "ITLB"}});
const Reg CoincidenceLength ("CoincidenceLengthT", RW::ReadWrite, TYPE::CH, {{"8", ""},{"524280", ""}}, ANSTYPE::NUM, "ns");
const Reg CoincidenceLengthSample ("CoincidenceLengthS", RW::ReadWrite); const Reg CoincidenceLengthSample ("CoincidenceLengthS", RW::ReadWrite);
const Reg ADCVetoWidth ("ADCVetoWidth", RW::ReadWrite); const Reg ADCVetoWidth ("ADCVetoWidth", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"524280", ""}}, ANSTYPE::NONE, "ns");
const Reg EnergySkimLowDiscriminator ("EnergySkimLowDiscriminator", RW::ReadWrite); const Reg EnergySkimLowDiscriminator ("EnergySkimLowDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}}, ANSTYPE::NUM);
const Reg EnergySkimHighDiscriminator ("EnergySkimHighDiscriminator", RW::ReadWrite); const Reg EnergySkimHighDiscriminator ("EnergySkimHighDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}}, ANSTYPE::NUM);
const Reg RecordLengthSample ("ChRecordLengthS", RW::ReadWrite); const Reg RecordLengthSample ("ChRecordLengthS", RW::ReadWrite);
const Reg PreTriggerSample ("ChPreTriggerS", RW::ReadWrite); const Reg PreTriggerSample ("ChPreTriggerS", RW::ReadWrite);

67
digiSettingsPanel.cpp
View File

@ -34,6 +34,7 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
} }
ID = 0; ID = 0;
enableSignalSlot = false;
QVBoxLayout * mainLayout = new QVBoxLayout(this); this->setLayout(mainLayout); QVBoxLayout * mainLayout = new QVBoxLayout(this); this->setLayout(mainLayout);
QTabWidget * tabWidget = new QTabWidget(this); mainLayout->addWidget(tabWidget); QTabWidget * tabWidget = new QTabWidget(this); mainLayout->addWidget(tabWidget);
@ -112,12 +113,11 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
lbTemp->setAlignment(Qt::AlignRight | Qt::AlignCenter); lbTemp->setAlignment(Qt::AlignRight | Qt::AlignCenter);
statusLayout->addWidget(lbTemp, 2, 0); statusLayout->addWidget(lbTemp, 2, 0);
const int nTemp = (int) DIGIPARA::DIG::TempSensADC.size(); for( int i = 0; i < 8; i++){
QLineEdit ** leTemp = new QLineEdit* [nTemp]; leTemp[iDigi][i] = new QLineEdit(tab);
for( int i = 0; i < nTemp; i++){ leTemp[iDigi][i]->setReadOnly(true);
leTemp[i] = new QLineEdit(tab); leTemp[iDigi][i]->setAlignment(Qt::AlignHCenter);
leTemp[i]->setEnabled(false); statusLayout->addWidget(leTemp[iDigi][i], 2, 1 + 2*i, 1, 2);
statusLayout->addWidget(leTemp[i], 2, 1 + 2*i, 1, 2);
} }
} }
@ -171,10 +171,10 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
lbClockSource->setAlignment(Qt::AlignRight); lbClockSource->setAlignment(Qt::AlignRight);
boardLayout->addWidget(lbClockSource, rowId, 0); boardLayout->addWidget(lbClockSource, rowId, 0);
QComboBox * comClockSource = new QComboBox(tab); cbbClockSource[iDigi] = new QComboBox(tab);
boardLayout->addWidget(comClockSource, rowId, 1, 1, 2); boardLayout->addWidget(cbbClockSource[iDigi], rowId, 1, 1, 2);
comClockSource->addItem("Internal 62.5 MHz"); cbbClockSource[iDigi]->addItem("Internal 62.5 MHz", "Internal");
comClockSource->addItem("Front Panel Clock input"); cbbClockSource[iDigi]->addItem("Front Panel Clock input", "FPClkIn");
//------------------------------------- //-------------------------------------
rowId ++; rowId ++;
@ -182,14 +182,11 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
lbStartSource->setAlignment(Qt::AlignRight); lbStartSource->setAlignment(Qt::AlignRight);
boardLayout->addWidget(lbStartSource, rowId, 0); boardLayout->addWidget(lbStartSource, rowId, 0);
QCheckBox * cbStartSource1 = new QCheckBox("EncodedClkIn", tab); QStringList startSourceText = {"EncodedClkIn", "SINlevel", "SINedge", "SWcmd", "LVDS"};
boardLayout->addWidget(cbStartSource1, rowId, 1); for( int i = 0; i < 5; i++){
QCheckBox * cbStartSource2 = new QCheckBox("SIN Level", tab); cbStartSource[iDigi][i] = new QCheckBox(startSourceText[i], tab);
boardLayout->addWidget(cbStartSource2, rowId, 2); boardLayout->addWidget(cbStartSource[iDigi][i], rowId, 1 + i);
QCheckBox * cbStartSource3 = new QCheckBox("SIN Edge", tab); }
boardLayout->addWidget(cbStartSource3, rowId, 3);
QCheckBox * cbStartSource4 = new QCheckBox("LVDS", tab);
boardLayout->addWidget(cbStartSource4, rowId, 4);
//------------------------------------- //-------------------------------------
rowId ++; rowId ++;
@ -588,12 +585,14 @@ void DigiSettingsPanel::LoadSettings(){
void DigiSettingsPanel::ShowSettingsToPanel(){ void DigiSettingsPanel::ShowSettingsToPanel(){
enableSignalSlot = false;
for (unsigned short j = 0; j < (unsigned short) infoIndex.size(); j++){ for (unsigned short j = 0; j < (unsigned short) infoIndex.size(); j++){
leInfo[ID][j]->setText(QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, infoIndex[j].second))); leInfo[ID][j]->setText(QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, infoIndex[j].second)));
} }
//--------- LED Status //--------- LED Status
unsigned int ledStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, 23).c_str()); unsigned int ledStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::LED_status).c_str());
for( int i = 0; i < 19; i++){ for( int i = 0; i < 19; i++){
if( (ledStatus >> i) & 0x1 ) { if( (ledStatus >> i) & 0x1 ) {
LEDStatus[ID][i]->setStyleSheet("background-color:green;"); LEDStatus[ID][i]->setStyleSheet("background-color:green;");
@ -603,7 +602,7 @@ void DigiSettingsPanel::ShowSettingsToPanel(){
} }
//--------- ACQ Status //--------- ACQ Status
unsigned int acqStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, 24).c_str()); unsigned int acqStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::ACQ_status).c_str());
for( int i = 0; i < 7; i++){ for( int i = 0; i < 7; i++){
if( (acqStatus >> i) & 0x1 ) { if( (acqStatus >> i) & 0x1 ) {
ACQStatus[ID][i]->setStyleSheet("background-color:green;"); ACQStatus[ID][i]->setStyleSheet("background-color:green;");
@ -612,7 +611,35 @@ void DigiSettingsPanel::ShowSettingsToPanel(){
} }
} }
//-------- temperature
for( int i = 0; i < 8; i++){
leTemp[ID][i]->setText(QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::TempSensADC[i])));
}
//-------- board settings
ReadCombBoxValue(cbbClockSource[ID], TYPE::DIG, DIGIPARA::DIG::ClockSource);
QString result = QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::StartSource));
QStringList resultList = result.remove(QChar(' ')).split("|");
qDebug() << resultList;
//for( int j = 0; j < 5; j++){
// cbStartSource[ID][j]->setChecked(false);
// for( int i = 0; resultList.count(); i++){
// if( resultList[i] == cbStartSource[ID][j]->text()) cbStartSource[ID][j]->setChecked(true);
// }
//}
enableSignalSlot = true;
} }
void DigiSettingsPanel::ReadCombBoxValue(QComboBox *cb, TYPE type, Reg para){
QString result = QString::fromStdString(digi[ID]->GetSettingValue(type, para));
int index = cb->findData(result);
if( index >= 0 && index < cb->count()) {
cb->setCurrentIndex(index);
}else{
qDebug() << result;
}
}

7
digiSettingsPanel.h
View File

@ -52,10 +52,15 @@ private:
void ShowSettingsToPanel(); void ShowSettingsToPanel();
bool enableSignalSlot;
QLineEdit * leInfo[MaxNumberOfChannel][12]; QLineEdit * leInfo[MaxNumberOfChannel][12];
QPushButton * LEDStatus[MaxNumberOfDigitizer][19]; QPushButton * LEDStatus[MaxNumberOfDigitizer][19];
QPushButton * ACQStatus[MaxNumberOfDigitizer][19]; QPushButton * ACQStatus[MaxNumberOfDigitizer][19];
QLineEdit * leTemp[MaxNumberOfDigitizer][8];
QComboBox * cbbClockSource[MaxNumberOfDigitizer];
QCheckBox * cbStartSource[MaxNumberOfDigitizer][5];
QPushButton *bn[MaxNumberOfChannel][MaxNumberOfChannel]; QPushButton *bn[MaxNumberOfChannel][MaxNumberOfChannel];
@ -86,6 +91,8 @@ private:
QLineEdit * leSettingFile[MaxNumberOfDigitizer]; QLineEdit * leSettingFile[MaxNumberOfDigitizer];
void ReadCombBoxValue(QComboBox * cb, TYPE type, Reg para );