add more data in Reg class
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@ -135,7 +135,7 @@ class Digitizer2Gen {
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void ReadAllSettings(); // read settings from digitier and save to memory
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bool SaveSettingsToFile(const char * saveFileName = NULL); // ReadAllSettings + text file
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bool LoadSettingsFromFile(const char * loadFileName = NULL); // Load settings, write to digitizer and save to memory
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std::string GetSettingValue(TYPE type, unsigned short index, int ch_index = -1) const {
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std::string GetSettingValue(TYPE type, unsigned short index, unsigned int ch_index = 0) const {
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switch(type){
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case TYPE::DIG: return boardSettings[index].GetValue();
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case TYPE::CH: return chSettings[ch_index][index].GetValue();
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@ -144,6 +144,30 @@ class Digitizer2Gen {
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}
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return "invalid";
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}
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std::string GetSettingValue(TYPE type, const Reg para, unsigned int ch_index = 0) const{
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switch(type){
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case TYPE::DIG:{
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for( int i = 0; i < (int) boardSettings.size(); i++){
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if( para.GetPara() == boardSettings[i].GetPara()){
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return boardSettings[i].GetValue();
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}
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}
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};break;
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case TYPE::CH:{
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for( int i = 0; i < (int) chSettings[ch_index].size(); i++){
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if( para.GetPara() == chSettings[ch_index][i].GetPara()){
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return chSettings[ch_index][i].GetValue();
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}
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}
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};break;
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case TYPE::VGA: return VGASetting[ch_index].GetValue();
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case TYPE::LVDS: return "not defined";
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default : return "invalid";
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}
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return "no such parameter";
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}
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};
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#endif
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417
DigiParameters.h
417
DigiParameters.h
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@ -5,6 +5,7 @@
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#include <string>
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#include <vector>
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enum ANSTYPE {NUM, STR, NONE};
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enum TYPE {CH, DIG, LVDS, VGA};
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enum RW { ReadOnly, WriteOnly, ReadWrite};
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@ -16,26 +17,45 @@ class Reg {
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TYPE type;
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RW readWrite; // true for read/write, false for read-only
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bool isCmd;
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ANSTYPE ansType;
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std::string answerUnit;
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std::vector<std::pair<std::string, std::string>> answer;
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public:
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Reg(){
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this->name = "";
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this->readWrite = RW::ReadWrite;
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this->type = TYPE::CH;
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this->isCmd = false;
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this->value = "";
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name = "";
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readWrite = RW::ReadWrite;
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type = TYPE::CH;
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isCmd = false;
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value = "";
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ansType = ANSTYPE::STR;
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answerUnit = "";
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answer.clear();
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}
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Reg(std::string para, RW readwrite, TYPE type = TYPE::CH, bool isCmd = false){
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Reg(std::string para, RW readwrite,
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TYPE type = TYPE::CH,
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std::vector<std::pair<std::string,std::string>> answer = {},
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ANSTYPE ansType = ANSTYPE::STR,
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std::string ansUnit = "",
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bool isCmd = false){
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this->name = para;
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this->readWrite = readwrite;
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this->type = type;
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this->isCmd = isCmd;
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this->value = "";
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this->ansType = ansType;
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this->answer = answer;
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this->answerUnit = ansUnit;
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}
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~Reg(){};
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void SetValue(std::string sv) { this->value = sv;}
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std::string GetValue() const { return value;}
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RW ReadWrite() const {return readWrite;}
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TYPE GetType() const {return type;}
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ANSTYPE GetAnswerType() const {return ansType;}
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std::string GetUnit() const {return answerUnit;}
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std::vector<std::pair<std::string,std::string>> GetAnswers() const {return answer;}
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std::string GetPara() const {return name;}
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std::string GetFullPara(int ch_index = -1) const {
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@ -76,8 +96,7 @@ class Reg {
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return "invalid"; break;
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}
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}
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RW ReadWrite() const {return readWrite;}
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TYPE GetType() const {return type;}
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operator std::string () const {return name;} // this allow Reg kaka("XYZ", true); std::string haha = kaka;
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@ -97,100 +116,152 @@ namespace DIGIPARA{
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///============== read only
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const Reg CupVer ("CupVer", RW::ReadOnly, TYPE::DIG);
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const Reg FPGA_firmwareVersion ("FPGA_FwVer", RW::ReadOnly, TYPE::DIG);
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const Reg FirmwareType ("FwType", RW::ReadOnly, TYPE::DIG);
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const Reg FirmwareType ("FwType", RW::ReadOnly, TYPE::DIG, {{"DPP_PHA", ""}, {"DPP_ZLE", ""}, {"DPP_PSD", ""}, {"DPP_DAW", ""}, {"DPP_OPEN", ""}, {"Scope", ""}});
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const Reg ModelCode ("ModelCode", RW::ReadOnly, TYPE::DIG);
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const Reg PBCode ("PBCode", RW::ReadOnly, TYPE::DIG);
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const Reg ModelName ("ModelName", RW::ReadOnly, TYPE::DIG);
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const Reg FromFactor ("FormFactor", RW::ReadOnly, TYPE::DIG);
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const Reg FamilyCode ("FamilyCode", RW::ReadOnly, TYPE::DIG);
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const Reg SerialNumber ("SerialNum", RW::ReadOnly, TYPE::DIG);
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const Reg PCBrev_MB ("PCBrev_MB", RW::ReadOnly, TYPE::DIG);
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const Reg PCBrev_PB ("PCBrev_PB", RW::ReadOnly, TYPE::DIG);
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const Reg FromFactor ("FormFactor", RW::ReadOnly, TYPE::DIG, {{"0", "VME"}, {"1", "VME64X"}, {"2", "DT"}});
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const Reg FamilyCode ("FamilyCode", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg SerialNumber ("SerialNum", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg PCBrev_MB ("PCBrev_MB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg PCBrev_PB ("PCBrev_PB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg DPP_License ("License", RW::ReadOnly, TYPE::DIG);
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const Reg DPP_LicenseStatus ("LicenseStatus", RW::ReadOnly, TYPE::DIG);
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const Reg DPP_LicenseRemainingTime ("LicenseRemainingTime", RW::ReadOnly, TYPE::DIG);
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const Reg NumberOfChannel ("NumCh", RW::ReadOnly, TYPE::DIG);
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const Reg ADC_bit ("ADC_Nbit", RW::ReadOnly, TYPE::DIG);
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const Reg ADC_SampleRate ("ADC_SamplRate", RW::ReadOnly, TYPE::DIG);
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const Reg InputDynamicRange ("InputRange", RW::ReadOnly, TYPE::DIG);
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const Reg InputType ("InputType", RW::ReadOnly, TYPE::DIG);
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const Reg InputImpedance ("Zin", RW::ReadOnly, TYPE::DIG);
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const Reg DPP_LicenseRemainingTime ("LicenseRemainingTime", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg NumberOfChannel ("NumCh", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "sec");
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const Reg ADC_bit ("ADC_Nbit", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM);
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const Reg ADC_SampleRate ("ADC_SamplRate", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "MS/s");
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const Reg InputDynamicRange ("InputRange", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Vpp");
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const Reg InputType ("InputType", RW::ReadOnly, TYPE::DIG, {{"0","Singled ended"}, {"1", "Differential"}});
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const Reg InputImpedance ("Zin", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Ohm");
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const Reg IPAddress ("IPAddress", RW::ReadOnly, TYPE::DIG);
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const Reg NetMask ("Netmask", RW::ReadOnly, TYPE::DIG);
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const Reg Gateway ("Gateway", RW::ReadOnly, TYPE::DIG);
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const Reg LED_status ("LedStatus", RW::ReadOnly, TYPE::DIG);
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const Reg ACQ_status ("AcquisitionStatus", RW::ReadOnly, TYPE::DIG);
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const Reg ACQ_status ("AcquisitionStatus", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "byte");
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const Reg MaxRawDataSize ("MaxRawDataSize", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensAirIn ("TempSensAirIn", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensAirOut ("TempSensAirOut", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensCore ("TempSensCore", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensFirstADC ("TempSensFirstADC", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensLastADC ("TempSensLastADC", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensHottestADC ("TempSensHottestADC", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC0 ("TempSensADC0", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC1 ("TempSensADC1", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC2 ("TempSensADC2", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC3 ("TempSensADC3", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC4 ("TempSensADC4", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC5 ("TempSensADC5", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC6 ("TempSensADC6", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensADC7 ("TempSensADC7", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensAirIn ("TempSensAirIn", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensAirOut ("TempSensAirOut", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensCore ("TempSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensFirstADC ("TempSensFirstADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensLastADC ("TempSensLastADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensHottestADC ("TempSensHottestADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC0 ("TempSensADC0", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC1 ("TempSensADC1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC2 ("TempSensADC2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC3 ("TempSensADC3", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC4 ("TempSensADC4", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC5 ("TempSensADC5", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC6 ("TempSensADC6", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg TempSensADC7 ("TempSensADC7", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7};
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const Reg TempSensDCDC ("TempSensDCDC", RW::ReadOnly, TYPE::DIG);
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const Reg VInSensDCDC ("VInSensDCDC", RW::ReadOnly, TYPE::DIG);
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const Reg VOutSensDCDC ("VOutSensDCDC", RW::ReadOnly, TYPE::DIG);
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const Reg IOutSensDCDC ("IOutSensDCDC", RW::ReadOnly, TYPE::DIG);
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const Reg FreqSensCore ("FreqSensCore", RW::ReadOnly, TYPE::DIG);
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const Reg DutyCycleSensDCDC ("DutyCycleSensDCDC", RW::ReadOnly, TYPE::DIG);
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const Reg SpeedSensFan1 ("SpeedSensFan1", RW::ReadOnly, TYPE::DIG);
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const Reg SpeedSensFan2 ("SpeedSensFan2", RW::ReadOnly, TYPE::DIG);
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const Reg TempSensDCDC ("TempSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "C");
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const Reg VInSensDCDC ("VInSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "V");
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const Reg VOutSensDCDC ("VOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "V");
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const Reg IOutSensDCDC ("IOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Amp");
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const Reg FreqSensCore ("FreqSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "Hz");
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const Reg DutyCycleSensDCDC ("DutyCycleSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "%");
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const Reg SpeedSensFan1 ("SpeedSensFan1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "rpm");
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const Reg SpeedSensFan2 ("SpeedSensFan2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::NUM, "rpm");
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const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG);
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const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG);
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const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG, {{"True", "No Error"}, {"False", "Error"}});
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///============= read write
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const Reg ClockSource ("ClockSource", RW::ReadWrite, TYPE::DIG);
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const Reg IO_Level ("IOlevel", RW::ReadWrite, TYPE::DIG);
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const Reg StartSource ("StartSource", RW::ReadWrite, TYPE::DIG);
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const Reg GlobalTriggerSource ("GlobalTriggerSource", RW::ReadWrite, TYPE::DIG);
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const Reg ClockSource ("ClockSource", RW::ReadWrite, TYPE::DIG, {{"Internal", "Internal Clock 62.5 MHz"},
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{"FPClkIn", "Front Plane Clock Input"}});
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const Reg IO_Level ("IOlevel", RW::ReadWrite, TYPE::DIG, {{"NIM", "NIM (0=0V, 1=-0.8V) "}, {"TTL", "TTL (0=0V, 1=3.3V)"}});
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const Reg StartSource ("StartSource", RW::ReadWrite, TYPE::DIG, {{"EncodedClkIn", "font panel CLK-IN/SYNC"},
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{"SINlevel", "S-IN Level"},
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{"SINedge", "S-IN Edge"},
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{"SWcmd", "Software"},
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{"LVDS", "LVDS"},
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{"PO", "Backplane"}});
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const Reg GlobalTriggerSource ("GlobalTriggerSource", RW::ReadWrite, TYPE::DIG,{{"TrgIn", "TRG-IN" },
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{"P0", "Back Plane" },
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{"SwTrg", "Software Trigger" },
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{"GPIO", "GPIO" },
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{"TestPulse", "Test Pulse" },
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{"LVDS", "LVDS"}});
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const Reg BusyInSource ("BusyInSource", RW::ReadWrite, TYPE::DIG);
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const Reg BusyInSource ("BusyInSource", RW::ReadWrite, TYPE::DIG, {{"SIN", "SIN"},
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{"GPIO", "GPIO"},
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{"LVDS", "LVDS"},
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{"Disabled","Disabled"}});
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//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
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const Reg EnableClockOutFrontPanel ("EnClockOutFP", RW::ReadWrite, TYPE::DIG);
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const Reg TrgOutMode ("TrgOutMode", RW::ReadWrite, TYPE::DIG);
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const Reg GPIOMode ("GPIOMode", RW::ReadWrite, TYPE::DIG);
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const Reg SyncOutMode ("SyncOutMode", RW::ReadWrite, TYPE::DIG);
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const Reg BoardVetoSource ("BoardVetoSource", RW::ReadWrite, TYPE::DIG);
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const Reg BoardVetoWidth ("BoardVetoWidth", RW::ReadWrite, TYPE::DIG);
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const Reg BoardVetoPolarity ("BoardVetoPolarity", RW::ReadWrite, TYPE::DIG);
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const Reg RunDelay ("RunDelay", RW::ReadWrite, TYPE::DIG);
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const Reg EnableAutoDisarmACQ ("EnAutoDisarmAcq", RW::ReadWrite, TYPE::DIG);
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const Reg EnableDataReduction ("EnDataReduction", RW::ReadWrite, TYPE::DIG);
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const Reg EnableStatisticEvents ("EnStatEvents", RW::ReadWrite, TYPE::DIG);
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const Reg VolatileClockOutDelay ("VolatileClockOutDelay", RW::ReadWrite, TYPE::DIG);
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const Reg PermanentClockOutDelay ("PermanentClockOutDelay", RW::ReadWrite, TYPE::DIG);
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const Reg TestPulsePeriod ("TestPulsePeriod", RW::ReadWrite, TYPE::DIG);
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const Reg TestPulseWidth ("TestPulseWidth", RW::ReadWrite, TYPE::DIG);
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const Reg TestPulseLowLevel ("TestPulseLowLevel", RW::ReadWrite, TYPE::DIG);
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const Reg TestPulseHighLevel ("TestPulseHighLevel", RW::ReadWrite, TYPE::DIG);
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const Reg EnableClockOutFrontPanel ("EnClockOutFP", RW::ReadWrite, TYPE::DIG, {{"True", "Enable"}, {"False", "Disabled"}});
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const Reg TrgOutMode ("TrgOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"TRGIN", "TRG-IN"},
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{"SwTrg", "Software Trigger"},
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{"LVDS", "LVDS"},
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{"Run", "Run Signal"},
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{"RefClk", "Reference Clock"},
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{"TestPulse", "Test Pulse"},
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{"Busy", "Busy Signal"},
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{"Fixed0", "0-level"},
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{"Fixed1", "1-level"},
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{"SyncIn", "SyncIn Signal"},
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{"SIN", "S-IN Signal"},
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{"GPIO", "GPIO Signal"},
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{"AccepTrg", "Acceped Trigger Signal"},
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{"TrgClk", "Trigger Clock"}});
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const Reg GPIOMode ("GPIOMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"TRGIN", "TRG-IN"},
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{"P0", "Back Plane"},
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{"SIN", "S-IN Signal"},
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{"LVDS", "LVDS Trigger"},
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{"SwTrg", "Software Trigger"},
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{"Run", "Run Signal"},
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{"RefClk", "Referece Clock"},
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{"TestPulse", "Test Pulse"},
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{"Busy", "Busy Signal"},
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{"Fixed0", "0-Level"},
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{"Fixed1", "1-Level"}});
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const Reg SyncOutMode ("SyncOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
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{"SyncIn", "Sync-In Signal"},
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{"TestPulse", "Test Pulse"},
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{"IntClk", "Internal Clock 62.5MHz"},
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{"Run", "Run Signal"} });
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const Reg BoardVetoSource ("BoardVetoSource", RW::ReadWrite, TYPE::DIG, {{"SIN", "S-IN"},
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{"LVDS", "LVDS"},
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{"GPIO", "GPIO"},
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{"P0", "Back Plane"},
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{"Disabled", "Disabled"} });
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const Reg BoardVetoWidth ("BoardVetoWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"34359738360", ""}}, ANSTYPE::NUM, "ns");
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const Reg BoardVetoPolarity ("BoardVetoPolarity", RW::ReadWrite, TYPE::DIG, {{"ActiveHigh", "Active when high"}, {"ActiveLow", "Active when low"}});
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const Reg RunDelay ("RunDelay", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"524280", ""}}, ANSTYPE::NUM, "ns");
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const Reg EnableAutoDisarmACQ ("EnAutoDisarmAcq", RW::ReadWrite, TYPE::DIG, {{"True", "Auto disarmed"}, {"False", "Disabled"}});
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const Reg EnableDataReduction ("EnDataReduction", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
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const Reg EnableStatisticEvents ("EnStatEvents", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
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const Reg VolatileClockOutDelay ("VolatileClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}}, ANSTYPE::NUM, "ps");
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const Reg PermanentClockOutDelay ("PermanentClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}}, ANSTYPE::NUM, "ps");
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const Reg TestPulsePeriod ("TestPulsePeriod", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}}, ANSTYPE::NUM, "ns");
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const Reg TestPulseWidth ("TestPulseWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}}, ANSTYPE::NUM, "ns");
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const Reg TestPulseLowLevel ("TestPulseLowLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}}, ANSTYPE::NUM, "ns");
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const Reg TestPulseHighLevel ("TestPulseHighLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}}, ANSTYPE::NUM, "ns");
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const Reg ErrorFlagMask ("ErrorFlagMask", RW::ReadWrite, TYPE::DIG);
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const Reg ErrorFlagDataMask ("ErrorFlagDataMask", RW::ReadWrite, TYPE::DIG);
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const Reg DACoutMode ("DACoutMode", RW::ReadWrite, TYPE::DIG);
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const Reg DACoutStaticLevel ("DACoutStaticLevel", RW::ReadWrite, TYPE::DIG);
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const Reg DACoutChSelect ("DACoutChSelect", RW::ReadWrite, TYPE::DIG);
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const Reg EnableOffsetCalibration ("EnOffsetCalibration", RW::ReadWrite, TYPE::DIG);
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||||
const Reg DACoutMode ("DACoutMode", RW::ReadWrite, TYPE::DIG, {{"Static", "DAC fixed level"},
|
||||
{"ChInput", "From Channel"},
|
||||
{"ChSum", "Sum of all Channels"},
|
||||
{"OverThrSum", "Number of Channels triggered"},
|
||||
{"Ramp", "14-bit counter"},
|
||||
{"Sin5MHz", "5 MHz Sin wave"},
|
||||
{"Square", "Test Pulse"}});
|
||||
const Reg DACoutStaticLevel ("DACoutStaticLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"16383", ""}}, ANSTYPE::NUM, "units");
|
||||
const Reg DACoutChSelect ("DACoutChSelect", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"64", ""}}, ANSTYPE::NUM);
|
||||
const Reg EnableOffsetCalibration ("EnOffsetCalibration", RW::ReadWrite, TYPE::DIG, {{"True", "Applied Cali."}, {"False", "No Cali."}});
|
||||
|
||||
/// ========== command
|
||||
const Reg Reset ("Reset", RW::WriteOnly, TYPE::DIG, true);
|
||||
const Reg ClearData ("ClearData", RW::WriteOnly, TYPE::DIG, true); // clear memory, setting not affected
|
||||
const Reg ArmACQ ("ArmAcquisition", RW::WriteOnly, TYPE::DIG, true);
|
||||
const Reg DisarmACQ ("DisarmAcquisition", RW::WriteOnly, TYPE::DIG, true);
|
||||
const Reg SoftwareStartACQ ("SwStartAcquisition", RW::WriteOnly, TYPE::DIG, true); // only when SwStart in StartSource
|
||||
const Reg SoftwareStopACQ ("SwStopAcquisition", RW::WriteOnly, TYPE::DIG, true); // stop ACQ, whatever start source
|
||||
const Reg SendSoftwareTrigger ("SendSWTrigger", RW::WriteOnly, TYPE::DIG, true); // only work when Swtrg in the GlobalTriggerSource
|
||||
const Reg ReloadCalibration ("ReloadCalibration", RW::WriteOnly, TYPE::DIG, true);
|
||||
const Reg Reset ("Reset", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
|
||||
const Reg ClearData ("ClearData", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // clear memory, setting not affected
|
||||
const Reg ArmACQ ("ArmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
|
||||
const Reg DisarmACQ ("DisarmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
|
||||
const Reg SoftwareStartACQ ("SwStartAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only when SwStart in StartSource
|
||||
const Reg SoftwareStopACQ ("SwStopAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // stop ACQ, whatever start source
|
||||
const Reg SendSoftwareTrigger ("SendSWTrigger", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only work when Swtrg in the GlobalTriggerSource
|
||||
const Reg ReloadCalibration ("ReloadCalibration", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
|
||||
|
||||
|
||||
const std::vector<Reg> AllSettings = {
|
||||
|
|
@ -279,13 +350,13 @@ namespace DIGIPARA{
|
|||
}
|
||||
|
||||
namespace VGA{
|
||||
const Reg VGAGain ("VGAGain", RW::ReadWrite, TYPE::VGA); // VX2745 only
|
||||
const Reg VGAGain ("VGAGain", RW::ReadWrite, TYPE::VGA, {{"0", ""},{"40", ""}}, ANSTYPE::NUM, "dB"); // VX2745 only
|
||||
}
|
||||
|
||||
namespace CH{
|
||||
|
||||
/// ========= red only
|
||||
const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly);
|
||||
const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::NUM, "Hz");
|
||||
const Reg ChannelStatus ("ChStatus", RW::ReadOnly);
|
||||
const Reg GainFactor ("GainFactor", RW::ReadOnly);
|
||||
const Reg ADCToVolts ("ADCToVolts", RW::ReadOnly);
|
||||
|
|
@ -297,53 +368,157 @@ namespace DIGIPARA{
|
|||
const Reg ChannelWaveCount ("ChWaveCnt", RW::ReadOnly);
|
||||
|
||||
/// ======= read write
|
||||
const Reg ChannelEnable ("ChEnable", RW::ReadWrite);
|
||||
const Reg DC_Offset ("DCOffset", RW::ReadWrite);
|
||||
const Reg TriggerThreshold ("TriggerThr", RW::ReadWrite);
|
||||
const Reg Polarity ("PulsePolarity", RW::ReadWrite);
|
||||
const Reg ChannelEnable ("ChEnable", RW::ReadWrite, TYPE::CH, {{"True", "Enabled"}, {"False", "Disabled"}});
|
||||
const Reg DC_Offset ("DCOffset", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"100", ""}}, ANSTYPE::NUM, "%");
|
||||
const Reg TriggerThreshold ("TriggerThr", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8191", ""}}, ANSTYPE::NUM);
|
||||
const Reg Polarity ("PulsePolarity", RW::ReadWrite, TYPE::CH, {{"Positive", "Pos. +"},{"Negative", "Neg. -"}});
|
||||
|
||||
const Reg WaveDataSource ("WaveDataSource", RW::ReadWrite);
|
||||
const Reg RecordLength ("ChRecordLengthT", RW::ReadWrite);
|
||||
const Reg PreTrigger ("ChPreTriggerT", RW::ReadWrite);
|
||||
const Reg WaveSaving ("WaveSaving", RW::ReadWrite);
|
||||
const Reg WaveResolution ("WaveResolution", RW::ReadWrite);
|
||||
const Reg TimeFilterRiseTime ("TimeFilterRiseTimeT", RW::ReadWrite);
|
||||
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite);
|
||||
const Reg EnergyFilterRiseTime ("EnergyFilterRiseTimeT", RW::ReadWrite);
|
||||
const Reg EnergyFilterFlatTop ("EnergyFilterFlatTopT", RW::ReadWrite);
|
||||
const Reg EnergyFilterPoleZero ("EnergyFilterPoleZeroT", RW::ReadWrite);
|
||||
const Reg EnergyFilterPeakingPosition ("EnergyFilterPeakingPosition", RW::ReadWrite);
|
||||
const Reg EnergyFilterPeakingAvg ("EnergyFilterPeakingAvg", RW::ReadWrite);
|
||||
const Reg EnergyFilterBaselineAvg ("EnergyFilterBaselineAvg", RW::ReadWrite);
|
||||
const Reg EnergyFilterBaselineGuard ("EnergyFilterBaselineGuardT", RW::ReadWrite);
|
||||
const Reg EnergyFilterFineGain ("EnergyFilterFineGain", RW::ReadWrite);
|
||||
const Reg EnergyFilterPileUpGuard ("EnergyFilterPileUpGuardT", RW::ReadWrite);
|
||||
const Reg EnergyFilterLowFreqFilter ("EnergyFilterLFLimitation", RW::ReadWrite);
|
||||
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite);
|
||||
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite);
|
||||
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite);
|
||||
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite);
|
||||
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite);
|
||||
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite);
|
||||
const Reg WaveDataSource ("WaveDataSource", RW::ReadWrite, TYPE::CH, {{"ADC_DATA", "Input ADC"},
|
||||
{"ADC_TEST_TOGGLE", "ADC produces TOGGLE signal"},
|
||||
{"ADC_TEST_RAMP", "ADC produces RAMP signal"},
|
||||
{"ADC_TEST_SIN", "ADC produce SIN signal"},
|
||||
{"Ramp", "Ramp generator"},
|
||||
{"SquareWave", "Test Pusle (Square Wave)"} });
|
||||
const Reg RecordLength ("ChRecordLengthT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"64800", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg PreTrigger ("ChPreTriggerT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"32000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg WaveSaving ("WaveSaving", RW::ReadWrite, TYPE::CH, {{"Always", "Always"}, {"OnRequest", "On Request"}});
|
||||
const Reg WaveResolution ("WaveResolution", RW::ReadWrite, TYPE::CH, {{"Res8", " 8 ns"},
|
||||
{"Res16","16 ns"},
|
||||
{"Res32","32 ns"},
|
||||
{"Res64","64 ns"}});
|
||||
const Reg TimeFilterRiseTime ("TimeFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"2000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg EnergyFilterRiseTime ("EnergyFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"13000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg EnergyFilterFlatTop ("EnergyFilterFlatTopT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"3000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg EnergyFilterPoleZero ("EnergyFilterPoleZeroT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"524000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg EnergyFilterPeakingPosition ("EnergyFilterPeakingPosition", RW::ReadWrite, TYPE::CH, {{"0", ""},{"100", ""}}, ANSTYPE::NUM, "%");
|
||||
const Reg EnergyFilterPeakingAvg ("EnergyFilterPeakingAvg", RW::ReadWrite, TYPE::CH, {{"OneShot", " 1 sample"},
|
||||
{"LowAVG", " 4 samples"},
|
||||
{"MediumAVG", "16 samples"},
|
||||
{"HighAVG", "64 samples"}});
|
||||
const Reg EnergyFilterBaselineAvg ("EnergyFilterBaselineAvg", RW::ReadWrite, TYPE::CH, {{"Fixed", " 0 sample"},
|
||||
{"VeryLow", " 16 samples"},
|
||||
{"Low", " 64 samples"},
|
||||
{"MediumLow", " 256 samples"},
|
||||
{"Medium", " 1024 samples"},
|
||||
{"MediumHigh"," 4096 samples"},
|
||||
{"High", "16384 samples"}});
|
||||
const Reg EnergyFilterBaselineGuard ("EnergyFilterBaselineGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg EnergyFilterFineGain ("EnergyFilterFineGain", RW::ReadWrite, TYPE::CH, {{"0", ""},{"10", ""}}, ANSTYPE::NUM);
|
||||
const Reg EnergyFilterPileUpGuard ("EnergyFilterPileUpGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"64000", ""}}, ANSTYPE::NUM);
|
||||
const Reg EnergyFilterLowFreqFilter ("EnergyFilterLFLimitation", RW::ReadWrite, TYPE::CH, {{"0", "Disabled"}, {"1", "Enabled"}});
|
||||
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
|
||||
{"TimeFilter", "Time Filter"},
|
||||
{"EnergyFilter", "Trapazoid"},
|
||||
{"EnergyFilterBase", "Trap. Baseline"},
|
||||
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
|
||||
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
|
||||
{"TimeFilter", "Time Filter"},
|
||||
{"EnergyFilter", "Trapazoid"},
|
||||
{"EnergyFilterBase", "Trap. Baseline"},
|
||||
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
|
||||
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
||||
{"TimeFilterArmed", "Time Filter Armed"},
|
||||
{"ReTriggerGuard", "ReTrigger Guard"},
|
||||
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
||||
{"EnergyFilterPeaking", "Peaking"},
|
||||
{"EnergyFilterPeakReady", "Peak Ready"},
|
||||
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
||||
{"EventPileUp", "Event Pile Up"},
|
||||
{"ADCSaturation", "ADC Saturate"},
|
||||
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
||||
{"PostSaturationEvent", "Post Sat. Event"},
|
||||
{"EnergylterSaturation", "Trap. Saturate"},
|
||||
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
||||
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
||||
{"TimeFilterArmed", "Time Filter Armed"},
|
||||
{"ReTriggerGuard", "ReTrigger Guard"},
|
||||
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
||||
{"EnergyFilterPeaking", "Peaking"},
|
||||
{"EnergyFilterPeakReady", "Peak Ready"},
|
||||
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
||||
{"EventPileUp", "Event Pile Up"},
|
||||
{"ADCSaturation", "ADC Saturate"},
|
||||
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
||||
{"PostSaturationEvent", "Post Sat. Event"},
|
||||
{"EnergylterSaturation", "Trap. Saturate"},
|
||||
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
||||
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
||||
{"TimeFilterArmed", "Time Filter Armed"},
|
||||
{"ReTriggerGuard", "ReTrigger Guard"},
|
||||
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
||||
{"EnergyFilterPeaking", "Peaking"},
|
||||
{"EnergyFilterPeakReady", "Peak Ready"},
|
||||
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
||||
{"EventPileUp", "Event Pile Up"},
|
||||
{"ADCSaturation", "ADC Saturate"},
|
||||
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
||||
{"PostSaturationEvent", "Post Sat. Event"},
|
||||
{"EnergylterSaturation", "Trap. Saturate"},
|
||||
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
||||
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
|
||||
{"TimeFilterArmed", "Time Filter Armed"},
|
||||
{"ReTriggerGuard", "ReTrigger Guard"},
|
||||
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
|
||||
{"EnergyFilterPeaking", "Peaking"},
|
||||
{"EnergyFilterPeakReady", "Peak Ready"},
|
||||
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
|
||||
{"EventPileUp", "Event Pile Up"},
|
||||
{"ADCSaturation", "ADC Saturate"},
|
||||
{"ADCSaturationProtection", "ADC Sat. Protection"},
|
||||
{"PostSaturationEvent", "Post Sat. Event"},
|
||||
{"EnergylterSaturation", "Trap. Saturate"},
|
||||
{"AcquisitionInhibit", "ACQ Inhibit"} });
|
||||
|
||||
const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1};
|
||||
const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3};
|
||||
|
||||
const Reg EventTriggerSource ("EventTriggerSource", RW::ReadWrite);
|
||||
const Reg ChannelsTriggerMask ("ChannelsTriggerMask", RW::ReadWrite);
|
||||
const Reg ChannelVetoSource ("ChannelVetoSource", RW::ReadWrite);
|
||||
const Reg WaveTriggerSource ("WaveTriggerSource", RW::ReadWrite);
|
||||
const Reg EventSelector ("EventSelector", RW::ReadWrite);
|
||||
const Reg WaveSelector ("WaveSelector", RW::ReadWrite);
|
||||
const Reg CoincidenceMask ("CoincidenceMask", RW::ReadWrite);
|
||||
const Reg AntiCoincidenceMask ("AntiCoincidenceMask", RW::ReadWrite);
|
||||
const Reg CoincidenceLength ("CoincidenceLengthT", RW::ReadWrite);
|
||||
|
||||
const Reg EventTriggerSource ("EventTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
|
||||
{"TRGIN", "TRG-IN"},
|
||||
{"SWTrigger", "Software Trigger"},
|
||||
{"ChSelfTrigger", "Channel Self-Trigger"},
|
||||
{"Ch64Trigger", "Channel 64-Trigger"},
|
||||
{"Disabled", "Disabled"}});
|
||||
const Reg ChannelsTriggerMask ("ChannelsTriggerMask", RW::ReadWrite, TYPE::CH, {}, ANSTYPE::STR, "64-bit" );
|
||||
const Reg ChannelVetoSource ("ChannelVetoSource", RW::ReadWrite, TYPE::CH, {{"BoardVeto", "Board Veto"},
|
||||
{"ADCOverSaturation", "ADC Over Saturation"},
|
||||
{"ADCUnderSaturation", "ADC Under Saturation"}});
|
||||
const Reg WaveTriggerSource ("WaveTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
|
||||
{"TRGIN", "TRG-IN"},
|
||||
{"ExternalInhibit", "External Inhibit"},
|
||||
{"ADCUnderSaturation", "ADC Under Saturation"},
|
||||
{"ADCOverSaturation", "ADC Over Saturation"},
|
||||
{"SWTrigger", "Software Trigger"},
|
||||
{"ChSelfTrigger", "Channel Self-Trigger"},
|
||||
{"Ch64Trigger", "Channel 64-Trigger"},
|
||||
{"Disabled", "Disabled"}});
|
||||
|
||||
const Reg EventSelector ("EventSelector", RW::ReadWrite, TYPE::CH, {{"All", "All"},
|
||||
{"Pileup", "Pile up"},
|
||||
{"EnergySkim", "Energy Skim"}});
|
||||
const Reg WaveSelector ("WaveSelector", RW::ReadWrite, TYPE::CH, {{"All", "All wave"},
|
||||
{"Pileup", "Only Pile up"},
|
||||
{"EnergySkim", "Only in Energy Skim Range"}});
|
||||
const Reg CoincidenceMask ("CoincidenceMask", RW::ReadWrite, TYPE::CH, {{"Disable", "Disabled"},
|
||||
{"Ch64Trigger", "Channel 64-Trigger"},
|
||||
{"TRGIN", "TRG-IN"},
|
||||
{"GlobalTriggerSource", "Global Trigger"},
|
||||
{"ITLA", "ITLA"},
|
||||
{"ITLB", "ITLB"}});
|
||||
const Reg AntiCoincidenceMask ("AntiCoincidenceMask", RW::ReadWrite, TYPE::CH,{{"Disable", "Disabled"},
|
||||
{"Ch64Trigger", "Channel 64-Trigger"},
|
||||
{"TRGIN", "TRG-IN"},
|
||||
{"GlobalTriggerSource", "Global Trigger"},
|
||||
{"ITLA", "ITLA"},
|
||||
{"ITLB", "ITLB"}});
|
||||
const Reg CoincidenceLength ("CoincidenceLengthT", RW::ReadWrite, TYPE::CH, {{"8", ""},{"524280", ""}}, ANSTYPE::NUM, "ns");
|
||||
const Reg CoincidenceLengthSample ("CoincidenceLengthS", RW::ReadWrite);
|
||||
|
||||
const Reg ADCVetoWidth ("ADCVetoWidth", RW::ReadWrite);
|
||||
const Reg ADCVetoWidth ("ADCVetoWidth", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"524280", ""}}, ANSTYPE::NONE, "ns");
|
||||
|
||||
const Reg EnergySkimLowDiscriminator ("EnergySkimLowDiscriminator", RW::ReadWrite);
|
||||
const Reg EnergySkimHighDiscriminator ("EnergySkimHighDiscriminator", RW::ReadWrite);
|
||||
const Reg EnergySkimLowDiscriminator ("EnergySkimLowDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}}, ANSTYPE::NUM);
|
||||
const Reg EnergySkimHighDiscriminator ("EnergySkimHighDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}}, ANSTYPE::NUM);
|
||||
|
||||
const Reg RecordLengthSample ("ChRecordLengthS", RW::ReadWrite);
|
||||
const Reg PreTriggerSample ("ChPreTriggerS", RW::ReadWrite);
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
|
|||
}
|
||||
|
||||
ID = 0;
|
||||
enableSignalSlot = false;
|
||||
|
||||
QVBoxLayout * mainLayout = new QVBoxLayout(this); this->setLayout(mainLayout);
|
||||
QTabWidget * tabWidget = new QTabWidget(this); mainLayout->addWidget(tabWidget);
|
||||
|
|
@ -112,12 +113,11 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
|
|||
lbTemp->setAlignment(Qt::AlignRight | Qt::AlignCenter);
|
||||
statusLayout->addWidget(lbTemp, 2, 0);
|
||||
|
||||
const int nTemp = (int) DIGIPARA::DIG::TempSensADC.size();
|
||||
QLineEdit ** leTemp = new QLineEdit* [nTemp];
|
||||
for( int i = 0; i < nTemp; i++){
|
||||
leTemp[i] = new QLineEdit(tab);
|
||||
leTemp[i]->setEnabled(false);
|
||||
statusLayout->addWidget(leTemp[i], 2, 1 + 2*i, 1, 2);
|
||||
for( int i = 0; i < 8; i++){
|
||||
leTemp[iDigi][i] = new QLineEdit(tab);
|
||||
leTemp[iDigi][i]->setReadOnly(true);
|
||||
leTemp[iDigi][i]->setAlignment(Qt::AlignHCenter);
|
||||
statusLayout->addWidget(leTemp[iDigi][i], 2, 1 + 2*i, 1, 2);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -171,10 +171,10 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
|
|||
lbClockSource->setAlignment(Qt::AlignRight);
|
||||
boardLayout->addWidget(lbClockSource, rowId, 0);
|
||||
|
||||
QComboBox * comClockSource = new QComboBox(tab);
|
||||
boardLayout->addWidget(comClockSource, rowId, 1, 1, 2);
|
||||
comClockSource->addItem("Internal 62.5 MHz");
|
||||
comClockSource->addItem("Front Panel Clock input");
|
||||
cbbClockSource[iDigi] = new QComboBox(tab);
|
||||
boardLayout->addWidget(cbbClockSource[iDigi], rowId, 1, 1, 2);
|
||||
cbbClockSource[iDigi]->addItem("Internal 62.5 MHz", "Internal");
|
||||
cbbClockSource[iDigi]->addItem("Front Panel Clock input", "FPClkIn");
|
||||
|
||||
//-------------------------------------
|
||||
rowId ++;
|
||||
|
|
@ -182,14 +182,11 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
|
|||
lbStartSource->setAlignment(Qt::AlignRight);
|
||||
boardLayout->addWidget(lbStartSource, rowId, 0);
|
||||
|
||||
QCheckBox * cbStartSource1 = new QCheckBox("EncodedClkIn", tab);
|
||||
boardLayout->addWidget(cbStartSource1, rowId, 1);
|
||||
QCheckBox * cbStartSource2 = new QCheckBox("SIN Level", tab);
|
||||
boardLayout->addWidget(cbStartSource2, rowId, 2);
|
||||
QCheckBox * cbStartSource3 = new QCheckBox("SIN Edge", tab);
|
||||
boardLayout->addWidget(cbStartSource3, rowId, 3);
|
||||
QCheckBox * cbStartSource4 = new QCheckBox("LVDS", tab);
|
||||
boardLayout->addWidget(cbStartSource4, rowId, 4);
|
||||
QStringList startSourceText = {"EncodedClkIn", "SINlevel", "SINedge", "SWcmd", "LVDS"};
|
||||
for( int i = 0; i < 5; i++){
|
||||
cbStartSource[iDigi][i] = new QCheckBox(startSourceText[i], tab);
|
||||
boardLayout->addWidget(cbStartSource[iDigi][i], rowId, 1 + i);
|
||||
}
|
||||
|
||||
//-------------------------------------
|
||||
rowId ++;
|
||||
|
|
@ -588,12 +585,14 @@ void DigiSettingsPanel::LoadSettings(){
|
|||
|
||||
void DigiSettingsPanel::ShowSettingsToPanel(){
|
||||
|
||||
enableSignalSlot = false;
|
||||
|
||||
for (unsigned short j = 0; j < (unsigned short) infoIndex.size(); j++){
|
||||
leInfo[ID][j]->setText(QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, infoIndex[j].second)));
|
||||
}
|
||||
|
||||
//--------- LED Status
|
||||
unsigned int ledStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, 23).c_str());
|
||||
unsigned int ledStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::LED_status).c_str());
|
||||
for( int i = 0; i < 19; i++){
|
||||
if( (ledStatus >> i) & 0x1 ) {
|
||||
LEDStatus[ID][i]->setStyleSheet("background-color:green;");
|
||||
|
|
@ -603,7 +602,7 @@ void DigiSettingsPanel::ShowSettingsToPanel(){
|
|||
}
|
||||
|
||||
//--------- ACQ Status
|
||||
unsigned int acqStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, 24).c_str());
|
||||
unsigned int acqStatus = atoi(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::ACQ_status).c_str());
|
||||
for( int i = 0; i < 7; i++){
|
||||
if( (acqStatus >> i) & 0x1 ) {
|
||||
ACQStatus[ID][i]->setStyleSheet("background-color:green;");
|
||||
|
|
@ -612,7 +611,35 @@ void DigiSettingsPanel::ShowSettingsToPanel(){
|
|||
}
|
||||
}
|
||||
|
||||
//-------- temperature
|
||||
for( int i = 0; i < 8; i++){
|
||||
leTemp[ID][i]->setText(QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::TempSensADC[i])));
|
||||
}
|
||||
|
||||
//-------- board settings
|
||||
ReadCombBoxValue(cbbClockSource[ID], TYPE::DIG, DIGIPARA::DIG::ClockSource);
|
||||
|
||||
QString result = QString::fromStdString(digi[ID]->GetSettingValue(TYPE::DIG, DIGIPARA::DIG::StartSource));
|
||||
QStringList resultList = result.remove(QChar(' ')).split("|");
|
||||
qDebug() << resultList;
|
||||
//for( int j = 0; j < 5; j++){
|
||||
// cbStartSource[ID][j]->setChecked(false);
|
||||
// for( int i = 0; resultList.count(); i++){
|
||||
// if( resultList[i] == cbStartSource[ID][j]->text()) cbStartSource[ID][j]->setChecked(true);
|
||||
// }
|
||||
//}
|
||||
|
||||
|
||||
enableSignalSlot = true;
|
||||
|
||||
}
|
||||
|
||||
void DigiSettingsPanel::ReadCombBoxValue(QComboBox *cb, TYPE type, Reg para){
|
||||
QString result = QString::fromStdString(digi[ID]->GetSettingValue(type, para));
|
||||
int index = cb->findData(result);
|
||||
if( index >= 0 && index < cb->count()) {
|
||||
cb->setCurrentIndex(index);
|
||||
}else{
|
||||
qDebug() << result;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,10 +52,15 @@ private:
|
|||
|
||||
void ShowSettingsToPanel();
|
||||
|
||||
bool enableSignalSlot;
|
||||
|
||||
QLineEdit * leInfo[MaxNumberOfChannel][12];
|
||||
QPushButton * LEDStatus[MaxNumberOfDigitizer][19];
|
||||
QPushButton * ACQStatus[MaxNumberOfDigitizer][19];
|
||||
QLineEdit * leTemp[MaxNumberOfDigitizer][8];
|
||||
|
||||
QComboBox * cbbClockSource[MaxNumberOfDigitizer];
|
||||
QCheckBox * cbStartSource[MaxNumberOfDigitizer][5];
|
||||
|
||||
|
||||
QPushButton *bn[MaxNumberOfChannel][MaxNumberOfChannel];
|
||||
|
|
@ -86,6 +91,8 @@ private:
|
|||
QLineEdit * leSettingFile[MaxNumberOfDigitizer];
|
||||
|
||||
|
||||
void ReadCombBoxValue(QComboBox * cb, TYPE type, Reg para );
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user