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rtang:v1.0
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compare: rtang:b79e125e889020bbe19e1af17b53cbd06966d03d
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rtang:master
rtang:v1.0

No commits in common. "c215d3cea114de91dae30a6fe7ed4883b028230e" and "b79e125e889020bbe19e1af17b53cbd06966d03d" have entirely different histories.
c215d3cea1 ... b79e125e88

6 changed files with 14 additions and 116 deletions
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45
ClassDigitizer2Gen.cpp
View File

@ -26,7 +26,6 @@ void Digitizer2Gen::Initialization(){
FPGAType = ""; FPGAType = "";
nChannels = 0; nChannels = 0;
ch2ns = 0; ch2ns = 0;
CupVer = 0;
outFileIndex = 0; outFileIndex = 0;
FinishedOutFilesSize = 0; FinishedOutFilesSize = 0;
@ -46,9 +45,6 @@ void Digitizer2Gen::Initialization(){
VGASetting[index] = PHA::VGA::VGAGain; VGASetting[index] = PHA::VGA::VGAGain;
LVDSSettings[index] = PHA::LVDS::AllSettings; LVDSSettings[index] = PHA::LVDS::AllSettings;
} }
for( int idx = 0; idx < 16; idx ++){
InputDelay[idx] = PHA::GROUP::InputDelay;
}
//build map //build map
for( int i = 0; i < (int) PHA::DIG::AllSettings.size(); i++) boardMap[PHA::DIG::AllSettings[i].GetPara()] = i; for( int i = 0; i < (int) PHA::DIG::AllSettings.size(); i++) boardMap[PHA::DIG::AllSettings[i].GetPara()] = i;
@ -135,7 +131,7 @@ std::string Digitizer2Gen::ReadValue(const Reg para, int ch_index, bool verbose
case TYPE::DIG : boardSettings[index].SetValue(ans); break; case TYPE::DIG : boardSettings[index].SetValue(ans); break;
case TYPE::VGA : VGASetting[ch_index].SetValue(ans); break; case TYPE::VGA : VGASetting[ch_index].SetValue(ans); break;
case TYPE::LVDS: LVDSSettings[ch_index][index].SetValue(ans);break; case TYPE::LVDS: LVDSSettings[ch_index][index].SetValue(ans);break;
case TYPE::GROUP: InputDelay[ch_index].SetValue(ans); break; case TYPE::GROUP: break; //^ GROUP is not implemented
} }
//printf("%s | %s | index %d | %s \n", para.GetFullPara(ch_index).c_str(), ans.c_str(), index, chSettings[ch_index][index].GetValue().c_str()); //printf("%s | %s | index %d | %s \n", para.GetFullPara(ch_index).c_str(), ans.c_str(), index, chSettings[ch_index][index].GetValue().c_str());
@ -187,7 +183,7 @@ bool Digitizer2Gen::WriteValue(const Reg para, std::string value, int ch_index){
// boardSettings[index].GetValue().c_str()); // boardSettings[index].GetValue().c_str());
}break; }break;
case TYPE::LVDS : LVDSSettings[ch_index][index].SetValue(value); break; case TYPE::LVDS : LVDSSettings[ch_index][index].SetValue(value); break;
case TYPE::GROUP : InputDelay[ch_index].SetValue(value); break; case TYPE::GROUP : break;
} }
} }
@ -236,7 +232,6 @@ int Digitizer2Gen::OpenDigitizer(const char * url){
FPGAVer = atoi(ReadValue(PHA::DIG::CupVer).c_str()); FPGAVer = atoi(ReadValue(PHA::DIG::CupVer).c_str());
nChannels = atoi(ReadValue(PHA::DIG::NumberOfChannel).c_str()); nChannels = atoi(ReadValue(PHA::DIG::NumberOfChannel).c_str());
ModelName = ReadValue(PHA::DIG::ModelName); ModelName = ReadValue(PHA::DIG::ModelName);
CupVer = atoi(ReadValue(PHA::DIG::CupVer).c_str());
int adcRate = atoi(ReadValue(PHA::DIG::ADC_SampleRate).c_str()); int adcRate = atoi(ReadValue(PHA::DIG::ADC_SampleRate).c_str());
ch2ns = 1000/adcRate; ch2ns = 1000/adcRate;
@ -260,9 +255,6 @@ int Digitizer2Gen::OpenDigitizer(const char * url){
VGASetting[index] = PHA::VGA::VGAGain; VGASetting[index] = PHA::VGA::VGAGain;
LVDSSettings[index] = PHA::LVDS::AllSettings; LVDSSettings[index] = PHA::LVDS::AllSettings;
} }
for( int idx = 0; idx < 16; idx ++ ){
InputDelay[idx] = PHA::GROUP::InputDelay;
}
//build map //build map
for( int i = 0; i < (int) PHA::DIG::AllSettings.size(); i++) boardMap[PHA::DIG::AllSettings[i].GetPara()] = i; for( int i = 0; i < (int) PHA::DIG::AllSettings.size(); i++) boardMap[PHA::DIG::AllSettings[i].GetPara()] = i;
@ -279,9 +271,6 @@ int Digitizer2Gen::OpenDigitizer(const char * url){
VGASetting[index] = PSD::VGA::VGAGain; VGASetting[index] = PSD::VGA::VGAGain;
LVDSSettings[index] = PSD::LVDS::AllSettings; LVDSSettings[index] = PSD::LVDS::AllSettings;
} }
for( int idx = 0; idx < 16; idx ++ ){
InputDelay[idx] = PSD::GROUP::InputDelay;
}
//build map //build map
for( int i = 0; i < (int) PSD::DIG::AllSettings.size(); i++) boardMap[PSD::DIG::AllSettings[i].GetPara()] = i; for( int i = 0; i < (int) PSD::DIG::AllSettings.size(); i++) boardMap[PSD::DIG::AllSettings[i].GetPara()] = i;
@ -1081,14 +1070,6 @@ void Digitizer2Gen::PrintBoardSettings(){
} }
} }
if( CupVer >= 2023091800 ){
for(int idx = 0; idx < 16 ; idx ++ ){
printf("%-45s %d %s\n", InputDelay[idx].GetFullPara(idx).c_str(),
InputDelay[idx].ReadWrite(),
InputDelay[idx].GetValue().c_str());
}
}
for( int i = 0; i < (int) LVDSSettings[0].size(); i++){ for( int i = 0; i < (int) LVDSSettings[0].size(); i++){
for( int index = 0; index < 4; index++){ for( int index = 0; index < 4; index++){
if( LVDSSettings[index][i].ReadWrite() == RW::WriteOnly) continue; if( LVDSSettings[index][i].ReadWrite() == RW::WriteOnly) continue;
@ -1148,8 +1129,6 @@ void Digitizer2Gen::ReadAllSettings(){
if( ModelName == "VX2745") for(int i = 0; i < 4 ; i ++) ReadValue(VGASetting[i], i); if( ModelName == "VX2745") for(int i = 0; i < 4 ; i ++) ReadValue(VGASetting[i], i);
if( CupVer >= 2023091800 ) for( int idx = 0; idx < 16; idx++) ReadValue(InputDelay[idx], idx, false);
for( int index = 0; index < 4; index++){ for( int index = 0; index < 4; index++){
for( int i = 0; i < (int) LVDSSettings[index].size(); i++){ for( int i = 0; i < (int) LVDSSettings[index].size(); i++){
if( LVDSSettings[index][i].ReadWrite() == RW::WriteOnly) continue; if( LVDSSettings[index][i].ReadWrite() == RW::WriteOnly) continue;
@ -1206,21 +1185,6 @@ int Digitizer2Gen::SaveSettingsToFile(const char * saveFileName, bool setReadOnl
count ++; count ++;
} }
if( CupVer >= 2023091800 ){
for( int idx = 0; idx < 16; idx ++){
totCount ++;
if( InputDelay[idx].GetValue() == "" ) {
printf(" No value for %s \n", InputDelay[idx].GetPara().c_str());
continue;
}
fprintf(saveFile, "%-45s!%d!%4d!%s\n", InputDelay[idx].GetFullPara(idx).c_str(),
InputDelay[idx].ReadWrite(),
9050 + idx,
InputDelay[idx].GetValue().c_str());
count ++;
}
}
if( ModelName == "VX2745" && FPGAType == DPPType::PHA) { if( ModelName == "VX2745" && FPGAType == DPPType::PHA) {
for(int i = 0; i < 4 ; i ++){ for(int i = 0; i < 4 ; i ++){
totCount ++; totCount ++;
@ -1352,10 +1316,8 @@ bool Digitizer2Gen::LoadSettingsFromFile(const char * loadFileName){
//printf("%s|%d|%d|%s\n", boardSettings[id-8000].GetFullPara().c_str(), //printf("%s|%d|%d|%s\n", boardSettings[id-8000].GetFullPara().c_str(),
// boardSettings[id-8000].ReadWrite(), id, // boardSettings[id-8000].ReadWrite(), id,
// boardSettings[id-8000].GetValue().c_str()); // boardSettings[id-8000].GetValue().c_str());
}else if ( 9000 <= id && id < 9050){ // vga }else{ // vga
VGASetting[id - 9000].SetValue(value); VGASetting[id - 9000].SetValue(value);
}else{ // group
if( CupVer >= 2023091800 ) InputDelay[id - 9050].SetValue(value);
} }
//printf("%s|%s|%d|%s|\n", para, readWrite, id, value); //printf("%s|%s|%d|%s|\n", para, readWrite, id, value);
if( std::strcmp(readWrite, "2") == 0 && isConnected) WriteValue(para, value, false); if( std::strcmp(readWrite, "2") == 0 && isConnected) WriteValue(para, value, false);
@ -1382,7 +1344,6 @@ std::string Digitizer2Gen::GetSettingValue(const Reg para, unsigned int ch_index
case TYPE::CH: return chSettings[ch_index][index].GetValue(); case TYPE::CH: return chSettings[ch_index][index].GetValue();
case TYPE::VGA: return VGASetting[ch_index].GetValue(); case TYPE::VGA: return VGASetting[ch_index].GetValue();
case TYPE::LVDS: return LVDSSettings[ch_index][index].GetValue(); case TYPE::LVDS: return LVDSSettings[ch_index][index].GetValue();
case TYPE::GROUP: return InputDelay[ch_index].GetValue();
default : return "invalid"; default : return "invalid";
} }
return "no such parameter"; return "no such parameter";

4
ClassDigitizer2Gen.h
View File

@ -12,7 +12,6 @@
#define MaxOutFileSize 2*1024*1024*1024 //2GB #define MaxOutFileSize 2*1024*1024*1024 //2GB
//#define MaxOutFileSize 20*1024*1024 //20MB //#define MaxOutFileSize 20*1024*1024 //20MB
#define MaxNumberOfChannel 64 #define MaxNumberOfChannel 64
#define MaxNumberOfGroup 16
#include "DigiParameters.h" #include "DigiParameters.h"
@ -33,7 +32,6 @@ class Digitizer2Gen {
char retValue[256]; char retValue[256];
unsigned short serialNumber; unsigned short serialNumber;
unsigned int CupVer;
std::string FPGAType; // look the DigitiParameter.h::PHA::DIG::FirwareType, DPP_PHA, DPP_ZLE, DPP_PSD, DPP_DAW, DPP_OPEN, and Scope std::string FPGAType; // look the DigitiParameter.h::PHA::DIG::FirwareType, DPP_PHA, DPP_ZLE, DPP_PSD, DPP_DAW, DPP_OPEN, and Scope
unsigned int FPGAVer; // for checking copy setting unsigned int FPGAVer; // for checking copy setting
unsigned short nChannels; unsigned short nChannels;
@ -64,7 +62,6 @@ class Digitizer2Gen {
std::vector<Reg> chSettings[MaxNumberOfChannel]; std::vector<Reg> chSettings[MaxNumberOfChannel];
std::vector<Reg> LVDSSettings[4]; std::vector<Reg> LVDSSettings[4];
Reg VGASetting[4]; Reg VGASetting[4];
Reg InputDelay[16];
std::map<std::string, int> boardMap; std::map<std::string, int> boardMap;
std::map<std::string, int> LVDSMap; std::map<std::string, int> LVDSMap;
@ -78,7 +75,6 @@ class Digitizer2Gen {
std::string GetFPGAType() const {return FPGAType;} std::string GetFPGAType() const {return FPGAType;}
std::string GetModelName() const {return ModelName;} std::string GetModelName() const {return ModelName;}
unsigned int GetFPGAVersion() const {return FPGAVer;} unsigned int GetFPGAVersion() const {return FPGAVer;}
unsigned int GetCupVer() const {return CupVer;}
void SetDummy(unsigned short sn); void SetDummy(unsigned short sn);
bool IsDummy() const {return isDummy;} bool IsDummy() const {return isDummy;}

35
DigiParameters.h
View File

@ -70,7 +70,7 @@ class Reg {
case TYPE::CH:{ case TYPE::CH:{
std::string haha = "/par/"; std::string haha = "/par/";
if( isCmd ){ if( isCmd ){
haha = "/cmd/"; // for SendChSWTrigger, not in GUI haha = "/cmd/";
} }
if( ch_index == -1 ){ if( ch_index == -1 ){
return "/ch/0..63" + haha + name; return "/ch/0..63" + haha + name;
@ -94,7 +94,7 @@ class Reg {
}; break; }; break;
case TYPE::GROUP:{ case TYPE::GROUP:{
if( ch_index == -1 ){ if( ch_index == -1 ){
return "/group/0..15/par/" + name; return "/group/0..16/par/" + name;
}else{ }else{
return "/group/" + std::to_string(ch_index) + "/par/" + name; return "/group/" + std::to_string(ch_index) + "/par/" + name;
} }
@ -173,6 +173,7 @@ namespace PHA{
const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::BINARY, "byte"); const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::BINARY, "byte");
const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG, {{"True", "No Error"}, {"False", "Error"}}); const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG, {{"True", "No Error"}, {"False", "Error"}});
//^ not impletemented
const Reg SPFLinkPresence ("SPFLinkPresence", RW::ReadOnly, TYPE::DIG, {{"True", "Inserted"}, {"False", "Disconnected"}}); const Reg SPFLinkPresence ("SPFLinkPresence", RW::ReadOnly, TYPE::DIG, {{"True", "Inserted"}, {"False", "Disconnected"}});
const Reg SPFLinkActive ("SPFLinkActive", RW::ReadOnly, TYPE::DIG, {{"True", "Active"}, {"False", "Deactive"}}); const Reg SPFLinkActive ("SPFLinkActive", RW::ReadOnly, TYPE::DIG, {{"True", "Active"}, {"False", "Deactive"}});
const Reg SPFLinkProtocol ("SPFLinkProtocal", RW::ReadOnly, TYPE::DIG, {{"Eth1G", "1 GB/s"}, {"Eth10G", "10 GB/s"}, {"CONET2", "Conet2"}}); const Reg SPFLinkProtocol ("SPFLinkProtocal", RW::ReadOnly, TYPE::DIG, {{"Eth1G", "1 GB/s"}, {"Eth10G", "10 GB/s"}, {"CONET2", "Conet2"}});
@ -352,9 +353,6 @@ namespace PHA{
SpeedSensFan2 , SpeedSensFan2 ,
ErrorFlags , ErrorFlags ,
BoardReady , BoardReady ,
// SPFLinkPresence ,
// SPFLinkActive ,
// SPFLinkProtocol ,
ClockSource , ClockSource ,
IO_Level , IO_Level ,
StartSource , StartSource ,
@ -404,7 +402,7 @@ namespace PHA{
} }
namespace GROUP{ namespace GROUP{
const Reg InputDelay ("InputDelay", RW::ReadWrite, TYPE::GROUP, {{"0",""}, {"100", ""}, {"0.000001", ""}}, ANSTYPE::INTEGER, "sec"); const Reg InputDelay ("InputDelay", RW::ReadWrite, TYPE::GROUP, {}, ANSTYPE::INTEGER, "S"); //^ Not impletemented.
} }
namespace VGA{ namespace VGA{
@ -429,9 +427,6 @@ namespace PHA{
namespace CH{ namespace CH{
/// ========= command
const Reg SendChSWTrigger ("SendChSWrigger", RW::WriteOnly, TYPE::CH, {}, ANSTYPE::NONE, "", true);
/// ========= red only /// ========= red only
const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::INTEGER, "Hz"); const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::INTEGER, "Hz");
const Reg ChannelStatus ("ChStatus", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR); const Reg ChannelStatus ("ChStatus", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
@ -446,7 +441,7 @@ namespace PHA{
/// ======= read write /// ======= read write
//^ not impletemented //^ not impletemented
const Reg SelfTriggerWidth ("SelfTriggerWidth", RW::ReadWrite, TYPE::CH, {{"0", ""},{"6000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns"); // not sure the max const Reg SelfTriggerWidh ("SelfTriggerWidth", RW::ReadWrite, TYPE::CH, {{"0", ""},{"6000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns"); // not sure the max
const Reg SignalOffset ("SignalOffset", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "uV"); // not sure the max const Reg SignalOffset ("SignalOffset", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "uV"); // not sure the max
@ -747,11 +742,6 @@ namespace PSD{
const Reg ErrorFlags = PHA::DIG::ErrorFlags; const Reg ErrorFlags = PHA::DIG::ErrorFlags;
const Reg BoardReady = PHA::DIG::BoardReady; const Reg BoardReady = PHA::DIG::BoardReady;
const Reg SPFLinkPresence = PHA::DIG::SPFLinkPresence;
const Reg SPFLinkActive = PHA::DIG::SPFLinkActive;
const Reg SPFLinkProtocol = PHA::DIG::SPFLinkProtocol;
///============= read write ///============= read write
//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG); //const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
const Reg ClockSource = PHA::DIG::ClockSource; const Reg ClockSource = PHA::DIG::ClockSource;
@ -862,9 +852,6 @@ namespace PSD{
SpeedSensFan2 , SpeedSensFan2 ,
ErrorFlags , ErrorFlags ,
BoardReady , BoardReady ,
// SPFLinkPresence ,
// SPFLinkActive ,
// SPFLinkProtocol ,
ClockSource , ClockSource ,
IO_Level , IO_Level ,
StartSource , StartSource ,
@ -912,10 +899,6 @@ namespace PSD{
} }
namespace GROUP{
const Reg InputDelay = PHA::GROUP::InputDelay;
}
namespace VGA{ namespace VGA{
const Reg VGAGain = PHA::VGA::VGAGain; const Reg VGAGain = PHA::VGA::VGAGain;
} }
@ -934,9 +917,6 @@ namespace PSD{
namespace CH{ namespace CH{
/// ========= command
const Reg SendChSWTrigger ("SendChSWrigger", RW::WriteOnly, TYPE::CH, {}, ANSTYPE::NONE, "", true);
/// ========= red only /// ========= red only
const Reg SelfTrgRate = PHA::CH::SelfTrgRate; const Reg SelfTrgRate = PHA::CH::SelfTrgRate;
const Reg ChannelStatus = PHA::CH::ChannelStatus; const Reg ChannelStatus = PHA::CH::ChannelStatus;
@ -949,11 +929,6 @@ namespace PSD{
const Reg ChannelWaveCount = PHA::CH::ChannelWaveCount; const Reg ChannelWaveCount = PHA::CH::ChannelWaveCount;
/// ======= read write /// ======= read write
//^ not impletemented
const Reg SelfTriggerWidth = PHA::CH::SelfTriggerWidth;
const Reg SignalOffset = PHA::CH::SignalOffset;
//^ impletemented
const Reg ChannelEnable = PHA::CH::ChannelEnable; const Reg ChannelEnable = PHA::CH::ChannelEnable;
const Reg DC_Offset = PHA::CH::DC_Offset; const Reg DC_Offset = PHA::CH::DC_Offset;
const Reg TriggerThreshold = PHA::CH::TriggerThreshold; const Reg TriggerThreshold = PHA::CH::TriggerThreshold;

31
digiSettingsPanel.cpp
View File

@ -107,14 +107,7 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
lab->setAlignment(Qt::AlignRight | Qt::AlignCenter); lab->setAlignment(Qt::AlignRight | Qt::AlignCenter);
leInfo[iDigi][j] = new QLineEdit(digiTab[iDigi]); leInfo[iDigi][j] = new QLineEdit(digiTab[iDigi]);
leInfo[iDigi][j]->setReadOnly(true); leInfo[iDigi][j]->setReadOnly(true);
leInfo[iDigi][j]->setText(QString::fromStdString(digi[iDigi]->ReadValue(infoIndex[j].second)));
Reg reg = infoIndex[j].second;
QString text = QString::fromStdString(digi[iDigi]->ReadValue(reg));
if( reg.GetPara() == PHA::DIG::ADC_SampleRate.GetPara() ) {
short tick2ns = 1000/ text.toInt();
text += " = " + QString::number(tick2ns, 'f', 1) + " ns" ;
}
leInfo[iDigi][j]->setText(text);
infoLayout->addWidget(lab, j%nRow, 2*(j/nRow)); infoLayout->addWidget(lab, j%nRow, 2*(j/nRow));
infoLayout->addWidget(leInfo[iDigi][j], j%nRow, 2*(j/nRow) +1); infoLayout->addWidget(leInfo[iDigi][j], j%nRow, 2*(j/nRow) +1);
} }
@ -788,23 +781,6 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
} }
if( digi[iDigi]->GetCupVer() >= 2023091800 ){
//^====================== Group = InputDelay
bdGroup[iDigi] = new QWidget(this);
bdTab->addTab(bdGroup[iDigi], "Input Delay");
QGridLayout * groupLayout = new QGridLayout(bdGroup[iDigi]);
groupLayout->setAlignment(Qt::AlignTop );
//LVDSLayout->setSpacing(2);
for(int k = 0; k < MaxNumberOfGroup; k ++){
SetupSpinBox(spbInputDelay[iDigi][k], PHA::GROUP::InputDelay, k, false, "ch : " + QString::number(4*k) + " - " + QString::number(4*k+3) + " [s] ", groupLayout, k/4, 2*(k%4));
spbInputDelay[iDigi][k]->setDecimals(6);
}
}else{
bdGroup[iDigi] = nullptr;
}
} }
{//^====================== Group channel settings {//^====================== Group channel settings
@ -2612,11 +2588,6 @@ void DigiSettingsPanel::UpdatePanelFromMemory(bool onlyStatus){
sbDACoutChSelect[ID]->setEnabled(false); sbDACoutChSelect[ID]->setEnabled(false);
} }
//------------ Group
for( int k = 0 ; k < MaxNumberOfGroup; k++){
FillSpinBoxValueFromMemory(spbInputDelay[ID][k], PHA::GROUP::InputDelay, k); // PHA = PSD
}
//@============================== Channel setting/ status //@============================== Channel setting/ status

4
digiSettingsPanel.h
View File

@ -65,7 +65,6 @@ private:
QWidget * bdVGA[MaxNumberOfDigitizer]; QWidget * bdVGA[MaxNumberOfDigitizer];
QWidget * bdLVDS[MaxNumberOfDigitizer]; QWidget * bdLVDS[MaxNumberOfDigitizer];
QWidget * bdITL[MaxNumberOfDigitizer]; QWidget * bdITL[MaxNumberOfDigitizer];
QWidget * bdGroup[MaxNumberOfDigitizer];
QGroupBox * box0[MaxNumberOfDigitizer]; QGroupBox * box0[MaxNumberOfDigitizer];
@ -207,9 +206,6 @@ private:
QLineEdit * chGainFactor[MaxNumberOfDigitizer][MaxNumberOfChannel]; QLineEdit * chGainFactor[MaxNumberOfDigitizer][MaxNumberOfChannel];
QLineEdit * chADCToVolts[MaxNumberOfDigitizer][MaxNumberOfChannel]; QLineEdit * chADCToVolts[MaxNumberOfDigitizer][MaxNumberOfChannel];
//--------------- Group settings
RSpinBox * spbInputDelay[MaxNumberOfDigitizer][MaxNumberOfGroup];
//--------------- Channel settings //--------------- Channel settings
RComboBox * cbChPick[MaxNumberOfDigitizer]; RComboBox * cbChPick[MaxNumberOfDigitizer];

1
mainwindow.cpp
View File

@ -952,7 +952,6 @@ bool MainWindow::CheckSOLARISpanelOK(){
return false; return false;
} }
LogMsg("Found <b>" + file.fileName() + "</b>. Setting up SOLARIS panel.");
mapping.clear(); mapping.clear();
std::vector<int> singleDigiMap; std::vector<int> singleDigiMap;
detType.clear(); detType.clear();