CAEN digitizer - Revision history

Rtang: /* Trapezoid Filter */

2024-11-02T18:42:55Z

Trapezoid Filter

← Older revision		Revision as of 14:42, 2 November 2024
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	Please see the following webpages : [https://nukephysik101.wordpress.com/2020/03/20/trapezoid-filter/ Trapezoid Filter] and [https://nukephysik101.wordpress.com/2022/05/11/trapezoid-filter-revisit/ Trapezoid Filter Revisit].		Please see the following webpages : [https://nukephysik101.wordpress.com/2020/03/20/trapezoid-filter/ Trapezoid Filter] and [https://nukephysik101.wordpress.com/2022/05/11/trapezoid-filter-revisit/ Trapezoid Filter Revisit].

	[[File:Trapezoid Filter.png\|~~500px~~]]		[[File:Trapezoid Filter.png\|700px]]

	=== Some settings and its meaning ===		=== Some settings and its meaning ===

Rtang: /* Channel Registers */

2024-11-02T18:33:01Z

Channel Registers

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	\| colspan="4" \| '''Other Settings'''		\| colspan="4" \| '''Other Settings'''
	\|-		\|-
	\| 18 \|\| Fine Gain \|\| 0x10C4 \|\| ~~It is not a simple sense of gain, related to DPP Algorithm Control~~ [~~5:0~~]		\| 18 \|\| Fine Gain \|\| 0x10C4 \|\| see [[#fine_gain_0x1nC4\|fine gate]]
	\|-		\|-
	\| 19 \|\| Events/Agg [G] \|\| 0x1034 \|\| Number of Events in a memory partition / aggregation		\| 19 \|\| Events/Agg [G] \|\| 0x1034 \|\| Number of Events in a memory partition / aggregation

Rtang: /* Channel Registers */

2024-11-02T18:32:14Z

Channel Registers

← Older revision		Revision as of 14:32, 2 November 2024
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	\| 4 \|\| Input Rise Time \|\| 0x1058 \|\| time constant for the RC-CR2		\| 4 \|\| Input Rise Time \|\| 0x1058 \|\| time constant for the RC-CR2
	\|-		\|-
	\| 5 \|\| DC Offset \|\| 0x1098 \|\| See [[#DC_offset_0x1n98]]		\| 5 \|\| DC Offset \|\| 0x1098 \|\| See [[#DC_offset_0x1n98\| DC offset]]
	\|-		\|-
	\| colspan="4" \| '''Trigger Settings'''		\| colspan="4" \| '''Trigger Settings'''
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	! Bit Range !! Name !!Description		! Bit Range !! Name !!Description
	\|-		\|-
	\| [5:0] \|\| Trapezoid Scaling \|\| ~~very complicate~~		\| [5:0] \|\| Trapezoid Scaling \|\| see [[#Trapezoid_Rescaling]]
	\|-		\|-
	\| [9:8] \|\| Decimation \|\| Average of the input signal. This applies to energy filter only.		\| [9:8] \|\| Decimation \|\| Average of the input signal. This applies to energy filter only.

Rtang: /* Channel Registers */

2024-11-02T18:31:10Z

Channel Registers

Rtang: /* Channel Registers */

2024-11-02T18:25:40Z

Channel Registers

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	\| 4 \|\| Input Rise Time \|\| 0x1058 \|\| time constant for the RC-CR2		\| 4 \|\| Input Rise Time \|\| 0x1058 \|\| time constant for the RC-CR2
	\|-		\|-
	\| 5 \|\| DC Offset \|\| 0x1098 \|\| See []		\| 5 \|\| DC Offset \|\| 0x1098 \|\| See [[#DC_offset_0x1n98]]
	\|-		\|-
	\| colspan="4" \| '''Trigger Settings'''		\| colspan="4" \| '''Trigger Settings'''

Rtang: /* Channel Registers */

2024-11-02T18:24:00Z

Channel Registers

← Older revision		Revision as of 14:24, 2 November 2024
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	! Number !! Name!! Address !! Description		! Number !! Name!! Address !! Description
	\|-		\|-
	\| 1 \|\| Record Length [G] \|\| 0x1029 \|\|		\| 1 \|\| Record Length [G] \|\| 0x1029 \|\| total time of a trace
	\|-		\|-
	\| 2 \|\| PreTrigger \|\| 0x1038 \|\|		\| 2 \|\| PreTrigger \|\| 0x1038 \|\| time before trigger
	\|-		\|-
	\| 3 \|\| Input Dynamic Range \|\| 0x1028 \|\|		\| 3 \|\| Input Dynamic Range \|\| 0x1028 \|\| Vpp to be 0.5V or 2.0V
	\|-		\|-
	\| 4 \|\| Input Rise Time \|\| 0x1058 \|\| time constant for the RC-CR2		\| 4 \|\| Input Rise Time \|\| 0x1058 \|\| time constant for the RC-CR2
	\|-		\|-
	\| 5 \|\| DC Offset \|\| 0x1098 \|\|		\| 5 \|\| DC Offset \|\| 0x1098 \|\| See []
	\|-		\|-
	\| colspan="4" \| '''Trigger Settings'''		\| colspan="4" \| '''Trigger Settings'''

Rtang: /* Channel Registers */

2024-11-02T18:20:43Z

Channel Registers

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	=== Channel Registers ===		=== Channel Registers ===
	There are 23 registers to control each (or coupled) channel for PHA firmware.		There are 23 registers to control each (or coupled) channel for PHA firmware. Settings with [G] mean '''grouped''', i.e. the setting are shared within a coupled channel. Settings with [W] means write-only.

	{\| class="wikitable"		{\| class="wikitable"

Rtang: /* PHA */

2024-11-02T18:17:01Z

PHA

← Older revision		Revision as of 14:17, 2 November 2024
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	[[File:Trapezoid Filter.png\|500px]]		[[File:Trapezoid Filter.png\|500px]]

			=== Some settings and its meaning ===

			[[File:Signal Scheme for PHA.png\|800px\|Signal Scheme for PHA, Taken and edited from CAEN Manual UM5960]]


	=== Channel Registers ===		=== Channel Registers ===
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	For example, a 40% DC offset, the register value is <math> \textrm{0xFFFF} \times 0.6 = 0x9999 </math>		For example, a 40% DC offset, the register value is <math> \textrm{0xFFFF} \times 0.6 = 0x9999 </math>


	~~=== Some settings and its meaning ===~~

	~~[[File:Signal Scheme for PHA.png\|800px\|Signal Scheme for PHA, Taken and edited from CAEN Manual UM5960]]~~

	=== Pile-up decision ===		=== Pile-up decision ===

Rtang: /* PHA */

2024-11-02T18:15:38Z

PHA

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 = DPP Firmware =
 == PHA ==
 === Channel Registers ===
@@ Line 836: / Line 848: @@
 For example, a 40% DC offset, the register value is <math> \textrm{0xFFFF} \times 0.6 = 0x9999 </math>
 === Some settings and its meaning ===

Rtang: /* DPP Firmware */

2024-11-02T18:14:32Z

DPP Firmware

← Older revision		Revision as of 14:14, 2 November 2024
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	\|}		\|}

			=== Some Special Settings ===
	Most of the register settings are trivial and east to understand, here is the list of special registers.		Most of the register settings are trivial and east to understand, here is the list of special registers.

	== Trapezoid Rescaling ==		==== Trapezoid Rescaling ====

	The register 0x1n80 (DPP Algorithm Control) bit [5:0] is the Trapezoid rescaling factor (SHF). It is calculated using the formula		The register 0x1n80 (DPP Algorithm Control) bit [5:0] is the Trapezoid rescaling factor (SHF). It is calculated using the formula
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	For example, if the rise time is 4000 ns ( = 250), decay time is 50 us ( = 3125 ), then then SHF = <math> \lfloor \log_2( 250 * 3125) \rfloor = 19 = \textrm{0x13} </math>. This is the standard scaling, meaning the internal trapezoid waveform (48 bits) is right-bit-shifted by 19 (i.e. >> 19 ) to a 15-bit value.		For example, if the rise time is 4000 ns ( = 250), decay time is 50 us ( = 3125 ), then then SHF = <math> \lfloor \log_2( 250 * 3125) \rfloor = 19 = \textrm{0x13} </math>. This is the standard scaling, meaning the internal trapezoid waveform (48 bits) is right-bit-shifted by 19 (i.e. >> 19 ) to a 15-bit value.

	== fine gain 0x1nC4 ==		==== fine gain 0x1nC4 ====

	fine gain = <math> f </math> is a 16-bit value (0 - 65535 = 0xFFFF ) calculated by		fine gain = <math> f </math> is a 16-bit value (0 - 65535 = 0xFFFF ) calculated by
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	The FSUDAQ always set <math> \alpha = 1 </math>		The FSUDAQ always set <math> \alpha = 1 </math>

	== DC offset 0x1n98 ==		==== DC offset 0x1n98 ====

	This is a 16-bit register. The percentage DC offset <math> \beta </math> to register value is <math> \textrm{0xFFFF} \times ( 1 - \beta ) </math>		This is a 16-bit register. The percentage DC offset <math> \beta </math> to register value is <math> \textrm{0xFFFF} \times ( 1 - \beta ) </math>

← Older revision		Revision as of 14:31, 2 November 2024
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	\| colspan="4" \| '''Trigger Settings'''		\| colspan="4" \| '''Trigger Settings'''
	\|-		\|-
	\| 6 \|\| ~~Trigger Threshold~~ \|\| ~~0x106c~~ \|\|		\| 9 \|\| RC-CR2 Smoothing Factor \|\| 0x1054 \|\| moving average of the RC-CR2 (2nd derivative) signal
	\|-		\|-
	\| 7 \|\| ~~Rise Time Validation Window~~ \|\| ~~0x1070~~ \|\|		\| 6 \|\| Trigger Threshold \|\| 0x106c \|\| When the RC-CR2 signal is over the threshold
	\|-		\|-
	\| 8 \|\| ~~Trigger Hold-off Width~~ \|\| ~~0x1074~~ \|\|		\| 7 \|\| Rise Time Validation Window \|\| 0x1070 \|\| If no trigger occurs in the window -> pileup/rej
	\|-		\|-
	\| 9 \|\| RC-~~CR2 Smoothing Factor~~ \|\| ~~0x1054~~ \|\|		\| 8 \|\| Trigger Hold-off Width \|\| 0x1074 \|\| Within this width, trigger disabled
	\|-		\|-
	\| 10 \|\| Shaped Trigger Width \|\| 0x1084 \|\|		\| 10 \|\| Shaped Trigger Width \|\| 0x1084 \|\| The width of the square pulse to go to trigger logic
	\|-		\|-
	\| 11 \|\| DPP Algorithm Control 2 [G] \|\| 0x10A0 \|\|		\| 11 \|\| DPP Algorithm Control 2 [G] \|\| 0x10A0 \|\| see table '''DPP Algorithm Control 2'''
	\|-		\|-
	\| colspan="4" \| '''Trapezoid Settings'''		\| colspan="4" \| '''Trapezoid Settings'''
	\|-		\|-
	\| 12 \|\| Trapezoid Rise Time \|\| 0x105C \|\|		\| 12 \|\| Trapezoid Rise Time \|\| 0x105C \|\|
	\|-		\|-
	\| 13 \|\| Trapezoid Flat Top \|\| 0x1060 \|\|		\| 13 \|\| Trapezoid Flat Top \|\| 0x1060 \|\|
	\|-		\|-
	\| 14 \|\| Peaking Time \|\| 0x1064 \|\|		\| 14 \|\| Peaking Time \|\| 0x1064 \|\| The time from trigger for energy calculation
	\|-		\|-
	\| 15 \|\| Decay Time \|\| 0x1068 \|\|		\| 15 \|\| Decay Time \|\| 0x1068 \|\| The input signal decay time. This control the pole-zero correction.
	\|-		\|-
	\| 16 \|\| Peak Hold-off \|\| 0x1078 \|\|		\| 16 \|\| Peak Hold-off \|\| 0x1078 \|\| This related to pile-up detection.
	\|-		\|-
	\| 17 \|\| DPP Algorithm Control \|\| 0x1080 \|\|		\| 17 \|\| DPP Algorithm Control \|\| 0x1080 \|\| see table '''DPP Algorithm Control'''
	\|-		\|-
	\| colspan="4" \| '''Other Settings'''		\| colspan="4" \| '''Other Settings'''