CAEN digitizer

Model

Model	Energy resolution	Sampling rate
V1725	14-bit	250MS/s
V1730	14-bit	500MS/s
V1740	12-bit	62.5 MS/s

DPP firmware

Both V1725 and V1730 can be equipped with the PHA (pulse-height analysis) or PSD (pulse-shape decimation) firmware.

From the programming point of view, the channel registers ( < 0x1XXX ) are very different for the two firmware, but the board registers (0x8000 to 0xFFFF) are almost identical.

required library

On Linux (Ubuntu 18.04+), two CAEN libraries are required to run the digitizers.

• CAENVMELib
• CAENComm

that would be enough for running the CAEN CoMPASS.

For custom programs, an additional library is needed

• CAENDigitizer

PLL (Phase-Locked-Loop) firmware

A digitizer need a proper PLL firmware to run.

If the PLL firmware is wrong (i.e. The PLL lock led is off ), you need to refresh the PLL firmware using the CAENUpgrader

The PLL file has the format of

V17XX_vcxo500_refYY_pll_outZZ.rbf

where

XX is the model type,

for example 25, 25S, 30, 40

YY is the ref clock,

for the master or stand alone digitizer, 50 (= 50 MHz ) is ok. 
for a slave, it must be 62_5. 

ZZ is the clock output,

for master or stand alone digitizer, 0 or 62_5 (= 62.5) are OK.
for a master that connect to a slave, it must be 62_5.
for a slave, that connect to an other slave, it must be 62_5

Synchronization of multiple digitizers

This is important when multiple digitizers are used. A digitizer using its internal clock (controlled by a switch on the board) is a designated Master. Synchronization means:

• Same source of clock
• Same phase (or constant difference in phase, it can be corrected by the Run delay (0x8170))
• Same starting time for ACQ

Notice that a Timer Reset can be done by writing the Software Clear register (0xEF28), but it does not guarantee all timers are clear at the same time. The Software clear is done whenever ACQ starts.

Master and Slaves Method

The CLK-out of the Master connects to the CLK-in of the slave in the daisy chain. And all slaves should use an external clock. The PLL firmware must be changed properly in order for the clocks of the master and the slaves to be locked and sync.

testing clocks

The TRG-OUT can be set with register 0x811C to be CLKOUT or CLK Phase. so that the synchronization can be checked.

TRG-IN/TRG-OUT daisy chain

Connect the TRG-IN (Master) to TRG-OUT (Slave). All slaves are set the ACQ start/stop on the TRG-IN (0x8100:[1:0]). The Master is set the ACQ star/stop to SW trigger, and the TRI-OUT is RUN (0x811C::[19:16]).

Once the master ACQ is started by SW, its TRG-OUT will send RUN signal and propagate to the slave TRG-IN that the slaves will be start/stop accordingly.

using S-IN with external TTL/NIM pulse

All master and slaves are set the ACQ start/stop to be S-IN, and TRG-OUT are S-IN (copy of S-IN). Master and slaves are connected TRG-OUT/S-IN daisy chain.

An external gate generator is needed to send an ACQ start signal to the master S-IN to start the data acquisition.

Triggering

Below is the Trigger Logic, the register is for DPP-PHA firmware.

Registers related to Trigger

Channel or Coupled Channel

PHA	PSD	Bit	Description
0x1n80	0x1n80	19:18	DPP Algorithm Control, Trigger Mode.
		24	DPP Algorithm Control, Disable self trigger
0x1n84	0x1n70		Shaped Trigger Width
0x1nA0	0x1084	2:0	DPP Algorithm Control 2, Local Shaped Trigger Mode
		6:4	DPP Algorithm Control 2, Local Trigger Validation Mode
		15:14	DPP Algorithm Control 2, Source of veto
0x1nDA	0x1nD4		Veto Width
0x8180 + 4n	0x810 + 4n		Trigger Validation Mask
	0x106C		Trigger Latency

Board

Register	! Bit	Description
0x810C		Global Trigger Mask or Logic
0x8110		Front Panel TRG-OUT Logic
0x811C	10	TRG-IN control
	11	TRG-IN to Mezzanines (Channel FPGA)

Single board

Scenario 0

No coincident, or self trigger.

0x1n80 0x00000 0xC0000 // set Trigger mode to Normal mode or Independent mode at DPP Algorithm Control.

Scenario 1

Coincident of ch-0 and ch-1 when both channels are within 1000 ns or 125 ticks.

Register Setting for DPP-PHA is:

0x1084  0x7D             // set the shaped trigger width is 1000 ns for channel 0
0x1184  0x7D             // set the shaped trigger width is 1000 ns for channel 1
0x1080  0x40000  0xC0000 // set channel-0 to be coindient mode 
0x1180  0x40000  0xC0000 // set channel-0 to be coindient mode
0x10A0  0x00     0x7     // Enable local Shaped Trigger, AND mode

Scenario 2

when ch-0 is fired and triggered, if ch-7 is also fired, record both ch-0 and ch-7. When ch-0 is fired and triggered, but if ch-7 has nothing, don't need to record ch-7 but only ch-0.

Register Setting for DPP-PHA in the free writefile:

//boardID address value mask
0-14-177 0x10A0 0x5     0x7      //DPP Algorithm Control 2 for channel-0, bit[2:0] = 101. Enable local Shaped Trigger, Mode is even channel of the coupled channel ONLY.
0-14-177 0x1780 0x40000 0xC0000  //DPP Algorithm Control for channel-7, bit[19:18] = 01. Trigger mode = Coincidence Mode 
0-14-177 0x1784 0xFF    0x3FF    //Shaped Trigger Width for channel-7, bit[9:0] = 00 1111 1111. Generate Shaped trigger of 255 * 16 ns.
0-14-177 0x16A0 0x50    0x70     //DPP Algorithm Control 2 for channel-6, bit[6:4] = 101. Enable local Trigger Validation, Mode is val0 = val1 = signal from mother board mask.
0-14-177 0x818C 0x1     0xFF     //Trigger Validation Mask for the 3rd (4*3 = C) coupled channels (ch-6-7). bit[7:0] =  0000 0001. Set trigger of coupled channel 3 from coupled channel 0. 

In FSUDAQ, in the Digitizer Settings Panel,

• Set the ch-0, Local Shaped trig. [G] to be The even Channel

• Set the ch-7, Trig Mode to be Coincident, Local Trig. Valid. [G] to be Equal

• In the board setting, go to the Trigger Mask tap, and set row 6-7, column 0-1.

Notice that the ch-6 will be triggred. To avoid this, can disable ch-6, or set ch-6 Trig. Mode to be Coincident.

Reading the bin file from CAEN CoMPASS

The CoMPASS can output *.bin data. The beginning of the file is a 2 bytes header. It must be in the form of 0xCAEx, where x indicate the energy format and waveform existence. After that,

block	bytes
Board	2
Channel	2
Timestamp	8
Energy	[x == 1, 2], [x == 2, 8], [x == 3, 10], [x == 4, 2]
Flags	4
Waveform code	1
number of samples	4
trace ...	2 * (number of samples)

If x < 8, there is no waveform.

A BinReader class can be found in here.

Data structure, Read-out, and buffer size

In the CAENDigitizer.h, the CAEN_DGTZ_READDATA() will read the buffer of the digitizer. For a single call of the function, ONE aggregate of data is read from the buffer and clear.

The number of events for an aggregate is set by register 0x1034. When set to zero, the digitizer (mysteriously) auto-set.

The data structure started with 4 words ( 1 word = 32 bits).

FSUDAQ

Main window of the FSUDAQ (Qt6)

Board Control of the FSUDAQ (Qt6)

https://fsunuc.physics.fsu.edu/git/rtang/FSUDAQ

The (idea of the) FSU DAQ is based on the BoxScore(code of BoxScore). The core is the digitizer class that directly controls and reads out the CAEN digitizer. The GUI of the DAQ uses CERN ROOT GUI elements.

The Goals for the DAQ are:

• support V1725, V1730, V1740 digitizers
• multi-thread readout and real-time time sorting (possibly events building)
• extendable to other digitizers and functionalities
• user-friendly (full GUI, limited terminal output)
• easy to maintain (avoid abstract coding and entirely objective programming)
• for Ubuntu 22.04 or equivalent
• binary output or root tree output

The development of this version is stopped at the end of 2022. The main reason is that it crashes when the mouse action on a histogram when ACQ is running. It is the problem of the CERN Root Drawing algorithm.

FSUDAQ (using Qt6)

The FSUDAQ GUI uses CERN ROOT Qt, which is based on Qt4. A new GUI is being made using Qt6. The FSUDAQ(Qt6) is very similar to the SOLARIS DAQ.

https://fsunuc.physics.fsu.edu/git/rtang/FSUDAQ_Qt6

In this development, the histogram (1D or 2D) will be developed based on QChart, which interaction with QChart during ACQ running is crash-free.

The Digitizer Class

The Digitizer class is ClassDigitizer.h/C. The class controls the digitizer by manipulating the register. And various types of digitizers are different by the registers. Thus, the class can control different types of digitizers without modification. The digitizer classes store the connection, board information, and a copy of the register. It provides an interface to better control the digitizer, for example, manipulate the bits for the control bit.

The digitizer classes directly write/read the registers in the digitizer. The advantage is complete control of the hardware and a simplified program that only 3 pieces are needed:

• WriteRegister()
• ReadRegister()
• Table of Register Address
• Load (Save) register setting from (to) a binary file

The drawback is that the buffer size must be calculated (a lazy man method is assigned 100 MB for the buffer?).

Register Address and Setting Binary File

The registers < 0x8000 are channel settings. For example, 0x1nXX is for channel-n, or 0x80XX is for writing to all channels. The registers >= 0x8000 are board settings.

For all types of digitizers, the register > 0x8000 registers are the same and have the same meaning.

Because the 2n and 2n+1 channels are paired ( like shared same memory ). There are some registers also paired. for example, the record length is the same for any paired channels, once the record length is set for any one of the paired channels, the record length of the other channel is also set.

A Setting uses 4 bytes (unsigned int) to store 32 bits of each register value. Using an array of size 2048 can store all register settings, which is only 8192 bytes. The following table shows the conversion.

Address Range	Comment	Setting Index	Example
0x1000 - 0x1FFF	Channel Setting	0x1XXX / 4	0x1020 -> 1032
0x8000 - 0x81FF	Board Setting	0x8XXX & 0x0FFF	0x8080 -> 32
0xEF00 - 0xEFFF	Other Board Setting	0xEXXX & 0x0FFF	0xEF04 -> 961
0xF000 - 0xFFFF	Read only board configuration	(0xFXXX & 0x0FFF) + 0x0200	0xF008 -> 520

The digitizer class provides a method to convert the setting binary to a text file. The following diagram illustrates the methods between board setting, setting in memory, and setting file

Buffer Size calculation

Board Aggregation. The digitizer data format, from CAEN manual.

Dual(paired) Channels Aggregation

The data stored in the digitizer can be retrieved using

CAEN_DGTZ_ReadData(int handle, CAEN_DGTZ_ReadMode_t mode, char *buffer, uint32_t *bufferSize);
typedef enum {
  CAEN_DGTZ_SLAVE_TERMINATED_READOUT_MBLT = 0,
  CAEN_DGTZ_SLAVE_TERMINATED_READOUT_2eVME = 1,
  CAEN_DGTZ_SLAVE_TERMINATED_READOUT_2eSST = 2,
  CAEN_DGTZ_POLLING_MBLT = 3,
  CAEN_DGTZ_POLLING_2eVME = 4,
  CAEN_DGTZ_POLLING_2eSST = 5,
} CAEN_DGTZ_ReadMode_t;

The data format of the buffer contains two parts: A whole chuck of the buffer can contain multiple board aggregation (depending on the value of 0xEF1C). Inside a board aggregation, there could be at most 8 Dual Channels Aggregation, depending on the channel mask. Each Dual Channels Aggregation can contain at most 511 measurements (set by 0x1n34). See the block diagrams on the

Each Board Aggregation has 4 words of header. 1 words = 4 bytes = 32 bits. Each Dual channel Aggregation has 2 words of header. after that is Ne events (0x1n34) for paired channels. In each measurement, there is 1 word of header, Sample/2 words for waveform, 1 word for Extra2 (if any), and 1 word for Energy, so total = (2 + Sample/2 + Extra), where Sample size is the Record Length = (0x1n20) * 8 ch. Extra is controlled by bit[17] of (0x8000), denote as (0x8000:17)

There is a maximum of 8 Dual Channel aggregations for 1 Board Aggregation for 16-channel digitizer. Thus, for 1 Board Aggregation, the max number of words is 4 + 8 * (n * (2 + Sample/2 + Extra)).

In Each readout, there can be more than 1 Board Aggregation (0xEF1C). The total buffer size (byte) needed is

$B=4N_{a}\left(4+\sum _{i=0}^{7}\left(2+N_{e}(i)C_{on}(i)(2+4N_{s}(i)+E_{2})\right)\right)$

where $N_{a}=$ bit value of 0xEF1C

$N_{e}(n)=$ bit value of 0x1n34, n = paired channel ID

$C_{on}(n)=$ Channel enabled mask of the paired channel n.

$N_{s}(n)=$ bit value of 0x1n20

$E_{2}=$ bit value of 0x8000, bit-17

However, this calculation is about factor 2 smaller than the CAEN's calculation in

CAEN_DGTZ_MallocReadoutBuffer(int handle, char **buffer, uint32_t *size);

The CAEN's formula for the buffer size is almost 2 times more.

$B_{c}=16+8N_{a}\left(2+\sum _{i=0}^{7}\left(2+N_{e}(i)C_{on}(i)(2+4N_{s}(i)+E_{2})\right)\right)$

Readout

The Event per Aggregation (0x1n34) are shared by the paired channels. for example, for 10 Event per Aggregation, the dual channel aggregation will only store 10 events for both paired channels.

The Maximum trigger for each dual channel is (Event per Aggregation) * (Aggregation per readout)

Also, it seems that, the maximum events in all paired channel is set by the maximum event number of the highest trigger rate channel. For example, I have 27 Hz input for channel 0,1, and 15. Although the Event per Aggregation was set to 60. the number event in the 0-1 dual channel aggregation is 27, which is the same number as the 14-15 dual channel.

Contact

Tsz Leung (Ryan) Tang mailto:rtang@fsu.edu