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added Register Class, aim for simplify the code algorithm

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carina@hades 2022-10-10 18:35:35 -04:00
parent 7e24189527
commit 31a39defe7
4 changed files with 420 additions and 29 deletions
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88
ClassDigitizer.cpp
View File

@ -663,26 +663,28 @@ int Digitizer::ProgramPHABoard(){
printf("======== program Channels PHA\n");
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::DecayTime + 0x7000 , 5000 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TrapezoidFlatTop + 0x7000 , 0x62 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TrapezoidRiseTime + 0x7000 , 6 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::PeakingTime + 0x7000 , 6 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::RCCR2SmoothingFactor + 0x7000 , 4 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::InputRiseTime + 0x7000 , 6 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TriggerThreshold + 0x7000 , 1000 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::PeakHoldOff + 0x7000 , 0x3E );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::TriggerHoldOffWidth + 0x7000 , 0x3E );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PHA::RiseTimeValidationWindow + 0x7000 , 0x0 );
uint32_t address;
address = Register::DPP::PHA::DecayTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 5000 );
address = Register::DPP::PHA::TrapezoidFlatTop; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x62 );
address = Register::DPP::PHA::TrapezoidRiseTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 6 );
address = Register::DPP::PHA::PeakingTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 6 );
address = Register::DPP::PHA::RCCR2SmoothingFactor; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 4 );
address = Register::DPP::PHA::InputRiseTime; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 6 );
address = Register::DPP::PHA::TriggerThreshold; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 1000 );
address = Register::DPP::PHA::PeakHoldOff; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x3E );
address = Register::DPP::PHA::TriggerHoldOffWidth; ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x3E );
address = Register::DPP::PHA::RiseTimeValidationWindow;ret |= CAEN_DGTZ_WriteRegister(handle, address + 0x7000 , 0x0 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::ChannelDCOffset + 0x7000 , 0xEEEE );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::PreTrigger + 0x7000 , 124 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::InputDynamicRange + 0x7000 , 0x0 );
ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(Register::DPP::ChannelDCOffset) + 0x7000 , 0xEEEE );
ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(Register::DPP::PreTrigger) + 0x7000 , 124 );
ret |= CAEN_DGTZ_WriteRegister(handle, (uint32_t)(Register::DPP::InputDynamicRange) + 0x7000 , 0x0 );
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::NumberEventsPerAggregate_G + 0x7000, 511);
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::AggregateOrganization, 0);
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::MaxAggregatePerBlockTransfer, 40);
ret |= CAEN_DGTZ_WriteRegister(handle, Register::DPP::DPPAlgorithmControl + 0x7000, 0xe30200f);
ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(Register::DPP::NumberEventsPerAggregate_G) + 0x7000, 511);
ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(Register::DPP::AggregateOrganization), 0);
ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(Register::DPP::MaxAggregatePerBlockTransfer), 40);
ret |= CAEN_DGTZ_WriteRegister(handle, (int32_t)(Register::DPP::DPPAlgorithmControl) + 0x7000, 0xe30200f);
if( ret != 0 ) { printf("==== set channels error.\n"); return 0;}
@ -1041,17 +1043,53 @@ void Digitizer::SaveSettingAsText(string fileName){
string name = "";
for( int i = 0; i < SETTINGSIZE ; i++){
name = "";
registerAddress = i * 4;
if( i < 0x0200 /4 ) {address = i * 4 + 0x8000; registerAddress = registerAddress; }
if( 0x0200 / 4 <= i && i < 0x0F00 /4 ) {address = i * 4 + 0xEE00; registerAddress = registerAddress; }/// EE00 == F000 - 0200
if( 0xF000 / 4 <= i && i < 0x1000 /4 ) {address = i * 4 + 0xE000; registerAddress = registerAddress; }
if( 0x1000 / 4 <= i ) { registerAddress = registerAddress & 0xF0FF ; }
if( i < 0x0200 /4 ) {address = i * 4 + 0x8000; registerAddress = address; }
if( 0x0200 / 4 <= i && i < 0x0300 /4 ) {address = i * 4 + 0xEE00; registerAddress = address; }/// EE00 == F000 - 0200
if( 0x0300 / 4 <= i && i < 0x0F00 /4 ) continue;
if( 0x0F00 / 4 <= i && i < 0x1000 /4 ) {address = i * 4 + 0xE000; registerAddress = address; }
if( 0x1000 / 4 <= i ) { address = i * 4; registerAddress = address & 0xF0FF ; }
///for TriggerValidationMask
if( i == ((0x8180 + 4) & 0x0FFF) / 4 ) {address = 0x8180 + 4; registerAddress = 0x8180;} /// 1
if( i == ((0x8180 + 8) & 0x0FFF) / 4 ) {address = 0x8180 + 8; registerAddress = 0x8180;} /// 2
if( i == ((0x8180 + 12) & 0x0FFF) / 4 ) {address = 0x8180 + 12; registerAddress = 0x8180;} /// 3
if( i == ((0x8180 + 16) & 0x0FFF) / 4 ) {address = 0x8180 + 16; registerAddress = 0x8180;} /// 4
if( i == ((0x8180 + 20) & 0x0FFF) / 4 ) {address = 0x8180 + 20; registerAddress = 0x8180;} /// 5
if( i == ((0x8180 + 24) & 0x0FFF) / 4 ) {address = 0x8180 + 24; registerAddress = 0x8180;} /// 6
if( i == ((0x8180 + 28) & 0x0FFF) / 4 ) {address = 0x8180 + 28; registerAddress = 0x8180;} /// 7
printf("==============%4d, 0x%04X , 0x%04X, 0x%04X \n", i, i*4, address, registerAddress);
if( DPPType == V1730_DPP_PSD_CODE || DPPType == V1730_DPP_PHA_CODE) {
for( int p = 0; p < (int) RegisterDPPList.size(); p++){
if( registerAddress == (uint32_t) RegisterDPPList[p] ) {
printf("0x%04X, 0x%04X, 0x%04X \n", i, registerAddress, (uint32_t) RegisterDPPList[p]);
name = RegisterDPPList[p].GetName();
}
}
}
if( DPPType == V1730_DPP_PHA_CODE) {
for( int p = 0; p < (int) RegisterPHAList.size(); p++){
if( registerAddress == (uint32_t) RegisterPHAList[p] ) name = RegisterPHAList[p].GetName();
}
}
if( DPPType == V1730_DPP_PSD_CODE) {
for( int p = 0; p < (int) RegisterPSDList.size(); p++){
if( registerAddress == (uint32_t) RegisterPSDList[p] ) name = RegisterPSDList[p].GetName();
}
}
if( name != "" ) fprintf( txtFile, "0x%04X %35s 0x%08X %d\n", address, name.c_str(), setting[i], setting[i]);
/****
if( DPPType == V1730_DPP_PSD_CODE || DPPType == V1730_DPP_PHA_CODE) {
switch( registerAddress ){
case Register::DPP::RecordLength_G : name = "DPP::RecordLength_G "; break;
case Register::DPP::InputDynamicRange : name = "DPP::InputDynamicRange "; break;
@ -1164,7 +1202,9 @@ void Digitizer::SaveSettingAsText(string fileName){
}
}
if( name != "" ) fprintf( txtFile, "0x%04X %35s 0x%08X %d\n", address, name.c_str(), setting[i], setting[i]);
***********/
}
}

3
ClassDigitizer.h
View File

@ -22,7 +22,7 @@ using namespace std;
class Digitizer{
public:
Digitizer();
Digitizer(); /// no digitizer open
Digitizer(int boardID, int portID = 0, bool program = false, bool verbose = false);
~Digitizer();
@ -39,6 +39,7 @@ class Digitizer{
uint32_t ReadRegister(uint32_t registerAddress, int ch = -1, string str = "");
///common for PHA and PSD digitizers
void SetDPPType (int type) { this->DPPType = type;} /// for manual override, or, digitizer does not open
void SetChannelMask (uint32_t mask);
void SetRecordLength (unsigned int ns, int ch = -1); /// when ch == -1, mean set all channels
void SetInputDynamicRange (unsigned int TwoVol_0_or_halfVol_1, int ch = -1);

341
RegisterAddress.h
View File

@ -1,16 +1,350 @@
#ifndef REGISTERADDRESS_H
#define REGISTERADDRESS_H
#include <vector>
///=======
/// All 0x1XXX registers are either indiviual or Group
/// Indiviual register are all independence
/// Group register, 2m and 2m+1 channels setting are shared. and the name will have _G as prefix
/// Most 0x8XXX registers are common, which share for all channel
#define GET_NAME(address) #address /// this give out the name, printf("%s", GET_NAME(Register::EventReadOutBuffer));
/// For adding Register, two things needed.
/// 1) add to the namepace
/// 2) add to the RegisterXXXList
/// The Reg Class has conversion operator
/// Reg haha("haha", 0x1234);
/// uint32_t papa = haha; /// papa = 0x1234
class Reg{
public:
Reg(std::string name, uint32_t address, char type = 0, bool group = 0 ){
this->name = name;
this->address = address;
this->type = type;
this->group = group;
};
~Reg(){};
operator uint32_t () const {return this->address;} /// this allows Reg kaka("kaka", 0x1234) uint32_t haha = kaka;
std::string GetName() const {return this->name;}
const char * GetNameChar() const {return this->name.c_str();}
uint32_t GetAddress() const {return this->address; }
char GetType() const {return this->type;}
bool GetGroup() const {return this->group;}
private:
uint32_t address;
std::string name;
char type; /// read/write = 0; read = 1; write = 2
bool group;
};
namespace Register {
const Reg EventReadOutBuffer("EventReadOutBuffer", 0x0000, 1); /// R
///========== Channel or Group
const Reg ChannelDummy32 ("ChannelDummy32" , 0x1024); /// R/W
const Reg InputDynamicRange ("InputDynamicRange" , 0x1028); /// R/W
const Reg ChannelPulseWidth ("ChannelPulseWidth" , 0x1070); /// R/W
const Reg ChannelTriggerThreshold ("ChannelTriggerThreshold" , 0x1080); /// R/W
const Reg CoupleSelfTriggerLogic_G ("CoupleSelfTriggerLogic_G" , 0x1084, 0 , 1); /// R/W
const Reg ChannelStatus_R ("ChannelStatus_R" , 0x1088, 1); /// R
const Reg AMCFirmwareRevision_R ("AMCFirmwareRevision_R" , 0x108C, 1); /// R
const Reg ChannelDCOffset ("ChannelDCOffset" , 0x1098); /// R/W
const Reg ChannelADCTemperature_R ("ChannelADCTemperature_R" , 0x10A8, 1); /// R
const Reg ChannelSelfTriggerRateMeter_R ("ChannelSelfTriggerRateMeter_R", 0x10EC, 1); /// R
///========== Board
const Reg BoardConfiguration ("BoardConfiguration" , 0x8000, 0); /// R/W
const Reg BufferOrganization ("BufferOrganization" , 0x800C, 0); /// R/W
const Reg CustomSize ("CustomSize" , 0x8020, 0); /// R/W
const Reg ADCCalibration_W ("ADCCalibration_W" , 0x809C, 2); /// W
const Reg AcquisitionControl ("AcquisitionControl" , 0x8100, 0); /// R/W
const Reg AcquisitionStatus_R ("AcquisitionStatus_R" , 0x8104, 1); /// R
const Reg SoftwareTrigger_W ("SoftwareTrigger_W" , 0x8108, 2); /// W
const Reg GlobalTriggerMask ("GlobalTriggerMask" , 0x810C, 0); /// R/W
const Reg FrontPanelTRGOUTEnableMask ("FrontPanelTRGOUTEnableMask" , 0x8110, 0); /// R/W
const Reg PostTrigger ("PostTrigger" , 0x8114, 0); /// R/W
const Reg LVDSIOData ("LVDSIOData" , 0x8118, 0); /// R/W
const Reg FrontPanelIOControl ("FrontPanelIOControl" , 0x811C, 0); /// R/W
const Reg ChannelEnableMask ("ChannelEnableMask" , 0x8120, 0); /// R/W
const Reg ROCFPGAFirmwareRevision_R ("ROCFPGAFirmwareRevision_R" , 0x8124, 1); /// R
const Reg EventStored_R ("EventStored_R" , 0x812C, 1); /// R
const Reg VoltageLevelModeConfig ("VoltageLevelModeConfig" , 0x8138, 0); /// R/W
const Reg SoftwareClockSync_W ("SoftwareClockSync_W" , 0x813C, 2); /// W
const Reg BoardInfo_R ("BoardInfo_R" , 0x8140, 1); /// R
const Reg AnalogMonitorMode ("AnalogMonitorMode" , 0x8144, 0); /// R/W
const Reg EventSize_R ("EventSize_R" , 0x814C, 1); /// R
const Reg FanSpeedControl ("FanSpeedControl" , 0x8168, 0); /// R/W
const Reg MemoryBufferAlmostFullLevel ("MemoryBufferAlmostFullLevel" , 0x816C, 0); /// R/W
const Reg RunStartStopDelay ("RunStartStopDelay" , 0x8170, 0); /// R/W
const Reg BoardFailureStatus_R ("BoardFailureStatus_R" , 0x8178, 1); /// R
const Reg FrontPanelLVDSIONewFeatures ("FrontPanelLVDSIONewFeatures" , 0x81A0, 0); /// R/W
const Reg BufferOccupancyGain ("BufferOccupancyGain" , 0x81B4, 0); /// R/W
const Reg ChannelsShutdown_W ("ChannelsShutdown_W" , 0x81C0, 2); /// W
const Reg ExtendedVetoDelay ("ExtendedVetoDelay" , 0x81C4, 0); /// R/W
const Reg ReadoutControl ("ReadoutControl" , 0xEF00, 0); /// R/W
const Reg ReadoutStatus_R ("ReadoutStatus_R" , 0xEF04, 1); /// R
const Reg BoardID ("BoardID" , 0xEF08, 0); /// R/W
const Reg MCSTBaseAddressAndControl ("MCSTBaseAddressAndControl" , 0xEF0C, 0); /// R/W
const Reg RelocationAddress ("RelocationAddress" , 0xEF10, 0); /// R/W
const Reg InterruptStatusID ("InterruptStatusID" , 0xEF14, 0); /// R/W
const Reg InterruptEventNumber ("InterruptEventNumber" , 0xEF18, 0); /// R/W
const Reg MaxAggregatePerBlockTransfer ("MaxAggregatePerBlockTransfer" , 0xEF1C, 0); /// R/W
const Reg Scratch ("Scratch" , 0xEF20, 0); /// R/W
const Reg SoftwareReset_W ("SoftwareReset_W" , 0xEF24, 2); /// W
const Reg SoftwareClear_W ("SoftwareClear_W" , 0xEF28, 2); /// W
///====== Common for PHA and PSD
namespace DPP {
const Reg RecordLength_G ("RecordLength_G" , 0x1020, 0, 1); /// R/W
const Reg InputDynamicRange ("InputDynamicRange" , 0x1028, 0); /// R/W
const Reg NumberEventsPerAggregate_G ("NumberEventsPerAggregate_G" , 0x1034, 0, 1); /// R/W
const Reg PreTrigger ("PreTrigger" , 0x1038, 0); /// R/W
const Reg TriggerThreshold ("TriggerThreshold" , 0x106C, 0); /// R/W
const Reg TriggerHoldOffWidth ("TriggerHoldOffWidth" , 0x1074, 0); /// R/W
const Reg DPPAlgorithmControl ("DPPAlgorithmControl" , 0x1080, 0); /// R/W
const Reg ChannelStatus_R ("ChannelStatus_R" , 0x1088, 1); /// R
const Reg AMCFirmwareRevision_R ("AMCFirmwareRevision_R" , 0x108C, 1); /// R
const Reg ChannelDCOffset ("ChannelDCOffset" , 0x1098, 0); /// R/W
const Reg ChannelADCTemperature_R ("ChannelADCTemperature_R" , 0x10A8, 1); /// R
const Reg IndividualSoftwareTrigger_W ("IndividualSoftwareTrigger_W" , 0x10C0, 2); /// W
const Reg VetoWidth ("VetoWidth" , 0x10D4, 0); /// R/W
/// I know there are many duplication, it is the design.
const Reg BoardConfiguration ("BoardConfiguration" , 0x8000, 0 ); /// R/W
const Reg AggregateOrganization ("AggregateOrganization" , 0x800C, 0 ); /// R/W
const Reg ADCCalibration_W ("ADCCalibration_W" , 0x809C, 2 ); /// W
const Reg ChannelShutdown_W ("ChannelShutdown_W" , 0x80BC, 2 ); /// W
const Reg AcquisitionControl ("AcquisitionControl" , 0x8100, 0 ); /// R/W
const Reg AcquisitionStatus_R ("AcquisitionStatus_R" , 0x8104, 1 ); /// R
const Reg SoftwareTrigger_W ("SoftwareTrigger_W" , 0x8108, 2 ); /// W
const Reg GlobalTriggerMask ("GlobalTriggerMask" , 0x810C, 0 ); /// R/W
const Reg FrontPanelTRGOUTEnableMask ("FrontPanelTRGOUTEnableMask" , 0x8110, 0 ); /// R/W
const Reg LVDSIOData ("LVDSIOData" , 0x8118, 0 ); /// R/W
const Reg FrontPanelIOControl ("FrontPanelIOControl" , 0x811C, 0 ); /// R/W
const Reg ChannelEnableMask ("ChannelEnableMask" , 0x8120, 0 ); /// R/W
const Reg ROCFPGAFirmwareRevision_R ("ROCFPGAFirmwareRevision_R" , 0x8124, 1 ); /// R
const Reg EventStored_R ("EventStored_R" , 0x812C, 1 ); /// R
const Reg VoltageLevelModeConfig ("VoltageLevelModeConfig" , 0x8138, 0 ); /// R/W
const Reg SoftwareClockSync_W ("SoftwareClockSync_W" , 0x813C, 2 ); /// W
const Reg BoardInfo_R ("BoardInfo_R" , 0x8140, 1 ); /// R
const Reg AnalogMonitorMode ("AnalogMonitorMode" , 0x8144, 0 ); /// R/W
const Reg EventSize_R ("EventSize_R" , 0x814C, 1 ); /// R
const Reg TimeBombDowncounter_R ("TimeBombDowncounter_R" , 0x8158, 1 ); /// R
const Reg FanSpeedControl ("FanSpeedControl" , 0x8168, 0 ); /// R/W
const Reg RunStartStopDelay ("RunStartStopDelay" , 0x8170, 0 ); /// R/W
const Reg BoardFailureStatus_R ("BoardFailureStatus_R" , 0x8178, 1 ); /// R
const Reg DisableExternalTrigger ("DisableExternalTrigger" , 0x817C, 0 ); /// R/W
const Reg TriggerValidationMask_G ("TriggerValidationMask_G" , 0x8180, 0 , 1); /// R/W,
const Reg FrontPanelLVDSIONewFeatures ("FrontPanelLVDSIONewFeatures" , 0x81A0, 0 ); /// R/W
const Reg BufferOccupancyGain ("BufferOccupancyGain" , 0x81B4, 0 ); /// R/W
const Reg ExtendedVetoDelay ("ExtendedVetoDelay" , 0x81C4, 0 ); /// R/W
const Reg ReadoutControl ("ReadoutControl" , 0xEF00, 0 ); /// R/W
const Reg ReadoutStatus_R ("ReadoutStatus_R" , 0xEF04, 1 ); /// R
const Reg BoardID ("BoardID" , 0xEF08, 0 ); /// R/W
const Reg MCSTBaseAddressAndControl ("MCSTBaseAddressAndControl" , 0xEF0C, 0 ); /// R/W
const Reg RelocationAddress ("RelocationAddress" , 0xEF10, 0 ); /// R/W
const Reg InterruptStatusID ("InterruptStatusID" , 0xEF14, 0 ); /// R/W
const Reg InterruptEventNumber ("InterruptEventNumber" , 0xEF18, 0 ); /// R/W
const Reg MaxAggregatePerBlockTransfer("MaxAggregatePerBlockTransfer", 0xEF1C, 0 ); /// R/W
const Reg Scratch ("Scratch" , 0xEF20, 0 ); /// R/W
const Reg SoftwareReset_W ("SoftwareReset_W" , 0xEF24, 2 ); /// W
const Reg SoftwareClear_W ("SoftwareClear_W" , 0xEF28, 2 ); /// W
const Reg ConfigurationReload_W ("ConfigurationReload_W" , 0xEF34, 2 ); /// W
const Reg ROMChecksum_R ("ROMChecksum_R" , 0xF000, 1 ); /// R
const Reg ROMChecksumByte2_R ("ROMChecksumByte2_R" , 0xF004, 1 ); /// R
const Reg ROMChecksumByte1_R ("ROMChecksumByte1_R" , 0xF008, 1 ); /// R
const Reg ROMChecksumByte0_R ("ROMChecksumByte0_R" , 0xF00C, 1 ); /// R
const Reg ROMConstantByte2_R ("ROMConstantByte2_R" , 0xF010, 1 ); /// R
const Reg ROMConstantByte1_R ("ROMConstantByte1_R" , 0xF014, 1 ); /// R
const Reg ROMConstantByte0_R ("ROMConstantByte0_R" , 0xF018, 1 ); /// R
const Reg ROM_C_Code_R ("ROM_C_Code_R" , 0xF01C, 1 ); /// R
const Reg ROM_R_Code_R ("ROM_R_Code_R" , 0xF020, 1 ); /// R
const Reg ROM_IEEE_OUI_Byte2_R ("ROM_IEEE_OUI_Byte2_R" , 0xF024, 1 ); /// R
const Reg ROM_IEEE_OUI_Byte1_R ("ROM_IEEE_OUI_Byte1_R" , 0xF028, 1 ); /// R
const Reg ROM_IEEE_OUI_Byte0_R ("ROM_IEEE_OUI_Byte0_R" , 0xF02C, 1 ); /// R
const Reg ROM_BoardVersion_R ("ROM_BoardVersion_R" , 0xF030, 1 ); /// R
const Reg ROM_BoardFromFactor_R ("ROM_BoardFromFactor_R" , 0xF034, 1 ); /// R
const Reg ROM_BoardIDByte1_R ("ROM_BoardIDByte1_R" , 0xF038, 1 ); /// R
const Reg ROM_BoardIDByte0_R ("ROM_BoardIDByte0_R" , 0xF03C, 1 ); /// R
const Reg ROM_PCB_rev_Byte3_R ("ROM_PCB_rev_Byte3_R" , 0xF040, 1 ); /// R
const Reg ROM_PCB_rev_Byte2_R ("ROM_PCB_rev_Byte2_R" , 0xF044, 1 ); /// R
const Reg ROM_PCB_rev_Byte1_R ("ROM_PCB_rev_Byte1_R" , 0xF048, 1 ); /// R
const Reg ROM_PCB_rev_Byte0_R ("ROM_PCB_rev_Byte0_R" , 0xF04C, 1 ); /// R
const Reg ROM_FlashType_R ("ROM_FlashType_R" , 0xF050, 1 ); /// R
const Reg ROM_BoardSerialNumByte1_R ("ROM_BoardSerialNumByte1_R" , 0xF080, 1 ); /// R
const Reg ROM_BoardSerialNumByte0_R ("ROM_BoardSerialNumByte0_R" , 0xF084, 1 ); /// R
const Reg ROM_VCXO_Type_R ("ROM_VCXO_Type_R" , 0xF088, 1 ); /// R
namespace PHA {
const Reg DataFlush_W ("DataFlush_W" , 0x103C, 2); /// W not sure
const Reg ChannelStopAcquisition ("ChannelStopAcquisition" , 0x1040); /// R/W not sure
const Reg RCCR2SmoothingFactor ("RCCR2SmoothingFactor" , 0x1054); /// R/W Trigger Filter smoothing, triggerSmoothingFactor
const Reg InputRiseTime ("InputRiseTime" , 0x1058); /// R/W OK
const Reg TrapezoidRiseTime ("TrapezoidRiseTime" , 0x105C); /// R/W OK
const Reg TrapezoidFlatTop ("TrapezoidFlatTop" , 0x1060); /// R/W OK
const Reg PeakingTime ("PeakingTime" , 0x1064); /// R/W OK
const Reg DecayTime ("DecayTime" , 0x1068); /// R/W OK
const Reg TriggerThreshold ("TriggerThreshold" , 0x106C); /// R/W OK
const Reg RiseTimeValidationWindow ("RiseTimeValidationWindow" , 0x1070); /// R/W OK
const Reg TriggerHoldOffWidth ("TriggerHoldOffWidth" , 0x1074); /// R/W OK
const Reg PeakHoldOff ("PeakHoldOff" , 0x1078); /// R/W OK
const Reg ShapedTriggerWidth ("ShapedTriggerWidth" , 0x1084); /// R/W not sure
const Reg DPPAlgorithmControl2_G ("DPPAlgorithmControl2_G" , 0x10A0, 0, 1); /// R/W OK
const Reg FineGain ("FineGain" , 0x10C4); /// R/W OK
}
namespace PSD {
const Reg CFDSetting ("CFDSetting" , 0x103C); /// R/W
const Reg ForcedDataFlush_W ("ForcedDataFlush_W" , 0x1040, 2); /// W
const Reg ChargeZeroSuppressionThreshold ("ChargeZeroSuppressionThreshold" , 0x1044); /// R/W
const Reg ShortGateWidth ("ShortGateWidth" , 0x1054); /// R/W
const Reg LongGateWidth ("LongGateWidth" , 0x1058); /// R/W
const Reg GateOffset ("GateOffset" , 0x105C); /// R/W
const Reg TriggerThreshold ("TriggerThreshold" , 0x1060); /// R/W
const Reg FixedBaseline ("FixedBaseline" , 0x1064); /// R/W
const Reg TriggerLatency ("TriggerLatency" , 0x106C); /// R/W
const Reg ShapedTriggerWidth ("ShapedTriggerWidth" , 0x1070); /// R/W
const Reg TriggerHoldOffWidth ("TriggerHoldOffWidth" , 0x1074); /// R/W
const Reg ThresholdForPSDCut ("ThresholdForPSDCut" , 0x1078); /// R/W
const Reg PurGapThreshold ("PurGapThreshold" , 0x107C); /// R/W
const Reg DPPAlgorithmControl2_G ("DPPAlgorithmControl2_G" , 0x1084, 0, 1); /// R/W
const Reg EarlyBaselineFreeze ("EarlyBaselineFreeze" , 0x10D8); /// R/W
}
}
};
const std::vector<Reg> RegisterPHAList = {
Register::DPP::PHA::DataFlush_W ,
Register::DPP::PHA::ChannelStopAcquisition ,
Register::DPP::PHA::RCCR2SmoothingFactor ,
Register::DPP::PHA::InputRiseTime ,
Register::DPP::PHA::TrapezoidRiseTime ,
Register::DPP::PHA::TrapezoidFlatTop ,
Register::DPP::PHA::PeakingTime ,
Register::DPP::PHA::DecayTime ,
Register::DPP::PHA::TriggerThreshold ,
Register::DPP::PHA::RiseTimeValidationWindow ,
Register::DPP::PHA::TriggerHoldOffWidth ,
Register::DPP::PHA::PeakHoldOff ,
Register::DPP::PHA::ShapedTriggerWidth ,
Register::DPP::PHA::DPPAlgorithmControl2_G ,
Register::DPP::PHA::FineGain
};
const std::vector<Reg> RegisterPSDList = {
Register::DPP::PSD::CFDSetting ,
Register::DPP::PSD::ForcedDataFlush_W ,
Register::DPP::PSD::ChargeZeroSuppressionThreshold ,
Register::DPP::PSD::ShortGateWidth ,
Register::DPP::PSD::LongGateWidth ,
Register::DPP::PSD::GateOffset ,
Register::DPP::PSD::TriggerThreshold ,
Register::DPP::PSD::FixedBaseline ,
Register::DPP::PSD::TriggerLatency ,
Register::DPP::PSD::ShapedTriggerWidth ,
Register::DPP::PSD::TriggerHoldOffWidth ,
Register::DPP::PSD::ThresholdForPSDCut ,
Register::DPP::PSD::PurGapThreshold ,
Register::DPP::PSD::DPPAlgorithmControl2_G ,
Register::DPP::PSD::EarlyBaselineFreeze
};
const std::vector<Reg> RegisterDPPList = {
Register::DPP::RecordLength_G ,
Register::DPP::InputDynamicRange ,
Register::DPP::NumberEventsPerAggregate_G ,
Register::DPP::PreTrigger ,
Register::DPP::TriggerThreshold ,
Register::DPP::TriggerHoldOffWidth ,
Register::DPP::DPPAlgorithmControl ,
Register::DPP::ChannelStatus_R ,
Register::DPP::AMCFirmwareRevision_R ,
Register::DPP::ChannelDCOffset ,
Register::DPP::ChannelADCTemperature_R ,
Register::DPP::IndividualSoftwareTrigger_W,
Register::DPP::VetoWidth ,
Register::DPP::BoardConfiguration ,
Register::DPP::AggregateOrganization ,
Register::DPP::ADCCalibration_W ,
Register::DPP::ChannelShutdown_W ,
Register::DPP::AcquisitionControl ,
Register::DPP::AcquisitionStatus_R ,
Register::DPP::SoftwareTrigger_W ,
Register::DPP::GlobalTriggerMask ,
Register::DPP::FrontPanelTRGOUTEnableMask ,
Register::DPP::LVDSIOData ,
Register::DPP::FrontPanelIOControl ,
Register::DPP::ChannelEnableMask ,
Register::DPP::ROCFPGAFirmwareRevision_R ,
Register::DPP::EventStored_R ,
Register::DPP::VoltageLevelModeConfig ,
Register::DPP::SoftwareClockSync_W ,
Register::DPP::BoardInfo_R ,
Register::DPP::AnalogMonitorMode ,
Register::DPP::EventSize_R ,
Register::DPP::TimeBombDowncounter_R ,
Register::DPP::FanSpeedControl ,
Register::DPP::RunStartStopDelay ,
Register::DPP::BoardFailureStatus_R ,
Register::DPP::DisableExternalTrigger ,
Register::DPP::TriggerValidationMask_G ,
Register::DPP::FrontPanelLVDSIONewFeatures ,
Register::DPP::BufferOccupancyGain ,
Register::DPP::ExtendedVetoDelay ,
Register::DPP::ReadoutControl ,
Register::DPP::ReadoutStatus_R ,
Register::DPP::BoardID ,
Register::DPP::MCSTBaseAddressAndControl ,
Register::DPP::RelocationAddress ,
Register::DPP::InterruptStatusID ,
Register::DPP::InterruptEventNumber ,
Register::DPP::MaxAggregatePerBlockTransfer,
Register::DPP::Scratch ,
Register::DPP::SoftwareReset_W ,
Register::DPP::SoftwareClear_W ,
Register::DPP::ConfigurationReload_W ,
Register::DPP::ROMChecksum_R ,
Register::DPP::ROMChecksumByte2_R ,
Register::DPP::ROMChecksumByte1_R ,
Register::DPP::ROMChecksumByte0_R ,
Register::DPP::ROMConstantByte2_R ,
Register::DPP::ROMConstantByte1_R ,
Register::DPP::ROMConstantByte0_R ,
Register::DPP::ROM_C_Code_R ,
Register::DPP::ROM_R_Code_R ,
Register::DPP::ROM_IEEE_OUI_Byte2_R ,
Register::DPP::ROM_IEEE_OUI_Byte1_R ,
Register::DPP::ROM_IEEE_OUI_Byte0_R ,
Register::DPP::ROM_BoardVersion_R ,
Register::DPP::ROM_BoardFromFactor_R ,
Register::DPP::ROM_BoardIDByte1_R ,
Register::DPP::ROM_BoardIDByte0_R ,
Register::DPP::ROM_PCB_rev_Byte3_R ,
Register::DPP::ROM_PCB_rev_Byte2_R ,
Register::DPP::ROM_PCB_rev_Byte1_R ,
Register::DPP::ROM_PCB_rev_Byte0_R ,
Register::DPP::ROM_FlashType_R ,
Register::DPP::ROM_BoardSerialNumByte1_R ,
Register::DPP::ROM_BoardSerialNumByte0_R ,
Register::DPP::ROM_VCXO_Type_R
};
/***************************
namespace Register {
const uint32_t EventReadOutBuffer = 0x0000; /// R
///========== Channel or Group
@ -68,7 +402,6 @@ namespace Register {
///====== Common for PHA and PSD
namespace DPP {
const uint32_t RecordLength_G = 0x1020; /// R/W
const uint32_t InputDynamicRange = 0x1028; /// R/W
const uint32_t NumberEventsPerAggregate_G = 0x1034; /// R/W
@ -184,7 +517,9 @@ namespace Register {
const uint32_t DPPAlgorithmControl2_G = 0x1084; /// R/W
const uint32_t EarlyBaselineFreeze = 0x10D8; /// R/W
}
}
}
}
*********************************/
#endif

17
test.cpp
View File

@ -80,7 +80,22 @@ long get_time(){
}
int main(int argc, char* argv[]){
//for( int p = 0; p < (int) RegisterDPPList.size(); p++){
// printf("0x%04X , %s\n", (uint32_t) RegisterDPPList[p], RegisterDPPList[p].GetNameChar());
//}
Digitizer * dig = new Digitizer;
dig->SetDPPType (V1730_DPP_PHA_CODE);
//dig->OpenSettingBinary("setting_323.bin");
dig->LoadSettingBinary("setting_323.bin");
//dig->PrintSettingFromMemory();
printf("##############################################################\n");
dig->SaveSettingAsText("haha.txt");
/*
const int nBoard = 2;
Digitizer **dig = new Digitizer *[nBoard];
@ -287,7 +302,7 @@ int main(int argc, char* argv[]){
*/
dig[0]->CloseDigitizer();
//dig[0]->CloseDigitizer();
return 0;
}