carina@hades
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354efc39b8
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added a more code frinedly SetSetting and GetSetting
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2022-08-29 18:06:12 -04:00 |
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carina@hades
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545aaec419
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improved ClassData and channelSetting
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2022-08-26 17:18:43 -04:00 |
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carina@hades
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7fb52da872
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kind of complete the board Setting UI
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2022-08-25 15:27:27 -04:00 |
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carina@hades
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7f720c1655
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edited boardSetting panel
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2022-08-24 17:50:21 -04:00 |
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carina@hades
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c264157a4a
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added PSD buffer decode
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2022-08-23 15:49:03 -04:00 |
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carina@hades
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4ead86783a
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many many changes
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2022-08-23 13:43:05 -04:00 |
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carina@hades
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c5fd1b1f65
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now have proper energy. testing timestamp roll over
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2022-08-18 17:34:28 -04:00 |
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carina@hades
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b2b5c75bb3
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created test_indep for testing code.
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2022-08-17 16:08:49 -04:00 |
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carina@hades
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be16a4369b
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snapshot, don't understand why triggered but zero energy
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2022-08-15 18:54:55 -04:00 |
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carina@hades
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0a6f866f7a
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also save TRG-OUT setting, change PHA default channel setting
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2022-08-12 18:13:54 -04:00 |
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carina@hades
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972c249076
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the price for adjust setting directly to register is need to manually allocate memory.
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2022-08-10 18:35:13 -04:00 |
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carina@hades
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1f943d8ded
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added PrintACQStatus
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2022-08-09 17:31:36 -04:00 |
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carina@hades
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223d751ba3
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EditByte in WriteRegister, coupled channel settings will set both channels
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2022-08-09 17:01:08 -04:00 |
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carina@hades
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f53601c063
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added setting binary control
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2022-08-09 16:02:45 -04:00 |
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athena
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304bebf467
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remove *.cxx and *.pcm from repository
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2022-08-06 01:38:01 -04:00 |
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athena
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cb722ba86b
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checked all PHA parameters. added DataClass.h and macro.h
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2022-08-05 18:15:50 -04:00 |
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splitPoleDAQ
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c0f9aa5eba
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change nSample to ns
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2022-08-05 16:32:46 -04:00 |
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splitPoleDAQ
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35278fc37b
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should focus on 1 board frist
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2022-08-04 18:02:03 -04:00 |
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splitPoleDAQ
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14731d5dea
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seperated DigitizerClass to DigitizerPHA, DigitizerPSD, add prototye of FSUDAQ
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2022-08-04 17:27:33 -04:00 |
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splitPoleDAQ
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240a35aba6
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building the digitizer class
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2022-08-03 19:00:41 -04:00 |
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