265 lines
13 KiB
C++
265 lines
13 KiB
C++
#ifndef REGISTERADDRESS_H
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#define REGISTERADDRESS_H
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///=======
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/// All 0x1XXX registers are either indiviual or Group
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/// Indiviual register are all independence
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/// Group register, 2m and 2m+1 channels setting are shared. and the name will have _G as prefix
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/// Most 0x8XXX registers are common, which share for all channel
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namespace Register {
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const uint32_t EventReadOutBuffer = 0x0000; /// R
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///========== Channel or Group
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const uint32_t ChannelDummy32 = 0x1024; /// R/W
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const uint32_t InputDynamicRange = 0x1028; /// R/W
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const uint32_t ChannelPulseWidth = 0x1070; /// R/W
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const uint32_t ChannelTriggerThreshold = 0x1080; /// R/W
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const uint32_t CoupleSelfTriggerLogic_G = 0x1084; /// R/W
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const uint32_t ChannelStatus = 0x1088; /// R
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const uint32_t AMCFirmwareRevision = 0x108C; /// R
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const uint32_t ChannelDCOffset = 0x1098; /// R/W
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const uint32_t ChannelADCTemperature = 0x10A8; /// R
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const uint32_t ChannelSelfTriggerRateMeter = 0x10EC; /// R
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///========== Board
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const uint32_t BoardConfiguration = 0x8000; /// R/W
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const uint32_t BufferOrganization = 0x800C; /// R/W
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const uint32_t CustomSize = 0x8020; /// R/W
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const uint32_t ADCCalibration = 0x809C; /// W
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const uint32_t AcquisitionControl = 0x8100; /// R/W
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const uint32_t AcquisitionStatus = 0x8104; /// R
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const uint32_t SoftwareTrigger = 0x8108; /// W
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const uint32_t GlobalTriggerMask = 0x810C; /// R/W
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const uint32_t FrontPanelTRGOUTEnableMask = 0x8110; /// R/W
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const uint32_t PostTrigger = 0x8114; /// R/W
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const uint32_t LVDSIOData = 0x8118; /// R/W
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const uint32_t FrontPanelIOControl = 0x811C; /// R/W
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const uint32_t ChannelEnableMask = 0x8120; /// R/W
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const uint32_t ROCFPGAFirmwareRevision = 0x8124; /// R
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const uint32_t EventStored = 0x812C; /// R
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const uint32_t VoltageLevelModeConfig = 0x8138; /// R/W
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const uint32_t SoftwareClockSync = 0x813C; /// W
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const uint32_t BoardInfo = 0x8140; /// R
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const uint32_t AnalogMonitorMode = 0x8144; /// R/W
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const uint32_t EventSize = 0x814C; /// R
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const uint32_t FanSpeedControl = 0x8168; /// R/W
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const uint32_t MemoryBufferAlmostFullLevel = 0x816C; /// R/W
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const uint32_t RunStartStopDelay = 0x8170; /// R/W
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const uint32_t BoardFailureStatus = 0x8178; /// R
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const uint32_t FrontPanelLVDSIONewFeatures = 0x81A0; /// R/W
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const uint32_t BufferOccupancyGain = 0x81B4; /// R/W
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const uint32_t ChannelsShutdown = 0x81C0; /// W
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const uint32_t ExtendedVetoDelay = 0x81C4; /// R/W
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const uint32_t ReadoutControl = 0xEF00; /// R/W
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const uint32_t ReadoutStatus = 0xEF04; /// R
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const uint32_t BoardID = 0xEF08; /// R/W
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const uint32_t MCSTBaseAddressAndControl = 0xEF0C; /// R/W
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const uint32_t RelocationAddress = 0xEF10; /// R/W
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const uint32_t InterruptStatusID = 0xEF14; /// R/W
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const uint32_t InterruptEventNumber = 0xEF18; /// R/W
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const uint32_t MaxAggregatePerBlockTransfer = 0xEF1C; /// R/W
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const uint32_t Scratch = 0xEF20; /// R/W
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const uint32_t SoftwareReset = 0xEF24; /// W
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const uint32_t SoftwareClear = 0xEF28; /// W
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///====== Common for PHA and PSD
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namespace DPP {
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const uint32_t RecordLength_G = 0x1020; /// R/W
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const uint32_t InputDynamicRange = 0x1028; /// R/W
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const uint32_t NumberEventsPerAggregate_G = 0x1034; /// R/W
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const uint32_t PreTrigger = 0x1038; /// R/W
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const uint32_t TriggerThreshold = 0x106C; /// R/W
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const uint32_t TriggerHoldOffWidth = 0x1074; /// R/W
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const uint32_t DPPAlgorithmControl = 0x1080; /// R/W
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const uint32_t ChannelStatus = 0x1088; /// R
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const uint32_t AMCFirmwareRevision = 0x108C; /// R
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const uint32_t ChannelDCOffset = 0x1098; /// R/W
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const uint32_t ChannelADCTemperature = 0x10A8; /// R
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const uint32_t IndividualSoftwareTrigger = 0x10C0; /// W
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const uint32_t VetoWidth = 0x10D4; /// R/W
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/// I know there are many duplication, it is the design.
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const uint32_t BoardConfiguration = 0x8000; /// R/W
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const uint32_t AggregateOrganization = 0x800C; /// R/W
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const uint32_t ADCCalibration = 0x809C; /// W
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const uint32_t ChannelShutdown = 0x80BC; /// W
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const uint32_t AcquisitionControl = 0x8100; /// R/W
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const uint32_t AcquisitionStatus = 0x8104; /// R
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const uint32_t SoftwareTrigger = 0x8108; /// W
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const uint32_t GlobalTriggerMask = 0x810C; /// R/W
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const uint32_t FrontPanelTRGOUTEnableMask = 0x8110; /// R/W
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const uint32_t LVDSIOData = 0x8118; /// R/W
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const uint32_t FrontPanelIOControl = 0x811C; /// R/W
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const uint32_t ChannelEnableMask = 0x8120; /// R/W
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const uint32_t ROCFPGAFirmwareRevision = 0x8124; /// R
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const uint32_t EventStored = 0x812C; /// R
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const uint32_t VoltageLevelModeConfig = 0x8138; /// R/W
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const uint32_t SoftwareClockSync = 0x813C; /// W
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const uint32_t BoardInfo = 0x8140; /// R /// [0:7] 0x0E = 725, 0x0B = 730, [8:15] 0x01 = 640 kSample, 0x08 = 5.12 MSample, [16:23] channel number
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const uint32_t AnalogMonitorMode = 0x8144; /// R/W
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const uint32_t EventSize = 0x814C; /// R
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const uint32_t TimeBombDowncounter = 0x8158; /// R
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const uint32_t FanSpeedControl = 0x8168; /// R/W
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const uint32_t RunStartStopDelay = 0x8170; /// R/W
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const uint32_t BoardFailureStatus = 0x8178; /// R
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const uint32_t DisableExternalTrigger = 0x817C; /// R/W
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const uint32_t TriggerValidationMask = 0x8180; /// R/W, 0x8180 + 4n
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const uint32_t FrontPanelLVDSIONewFeatures = 0x81A0; /// R/W
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const uint32_t BufferOccupancyGain = 0x81B4; /// R/W
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const uint32_t ExtendedVetoDelay = 0x81C4; /// R/W
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const uint32_t ReadoutControl = 0xEF00; /// R/W
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const uint32_t ReadoutStatus = 0xEF04; /// R
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const uint32_t BoardID = 0xEF08; /// R/W /// Geo address on VME crate
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const uint32_t MCSTBaseAddressAndControl = 0xEF0C; /// R/W
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const uint32_t RelocationAddress = 0xEF10; /// R/W
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const uint32_t InterruptStatusID = 0xEF14; /// R/W
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const uint32_t InterruptEventNumber = 0xEF18; /// R/W
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const uint32_t MaxAggregatePerBlockTransfer = 0xEF1C; /// R/W
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const uint32_t Scratch = 0xEF20; /// R/W
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const uint32_t SoftwareReset = 0xEF24; /// W
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const uint32_t SoftwareClear = 0xEF28; /// W
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const uint32_t ConfigurationReload = 0xEF34; /// W
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const uint32_t ROMChecksum = 0xF000; /// R
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const uint32_t ROMChecksumByte2 = 0xF004; /// R
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const uint32_t ROMChecksumByte1 = 0xF008; /// R
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const uint32_t ROMChecksumByte0 = 0xF00C; /// R
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const uint32_t ROMConstantByte2 = 0xF010; /// R
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const uint32_t ROMConstantByte1 = 0xF014; /// R
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const uint32_t ROMConstantByte0 = 0xF018; /// R
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const uint32_t ROM_C_Code = 0xF01C; /// R
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const uint32_t ROM_R_Code = 0xF020; /// R
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const uint32_t ROM_IEEE_OUI_Byte2 = 0xF024; /// R
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const uint32_t ROM_IEEE_OUI_Byte1 = 0xF028; /// R
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const uint32_t ROM_IEEE_OUI_Byte0 = 0xF02C; /// R
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const uint32_t ROM_BoardVersion = 0xF030; /// R
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const uint32_t ROM_BoardFromFactor = 0xF034; /// R
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const uint32_t ROM_BoardIDByte1 = 0xF038; /// R
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const uint32_t ROM_BoardIDByte0 = 0xF03C; /// R
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const uint32_t ROM_PCB_rev_Byte3 = 0xF040; /// R
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const uint32_t ROM_PCB_rev_Byte2 = 0xF044; /// R
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const uint32_t ROM_PCB_rev_Byte1 = 0xF048; /// R
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const uint32_t ROM_PCB_rev_Byte0 = 0xF04C; /// R
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const uint32_t ROM_FlashType = 0xF050; /// R
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const uint32_t ROM_BoardSerialNumByte1 = 0xF080; /// R
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const uint32_t ROM_BoardSerialNumByte0 = 0xF084; /// R
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const uint32_t ROM_VCXO_Type = 0xF088; /// R
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namespace PHA {
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const uint32_t DataFlush = 0x103C; /// W not sure
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const uint32_t ChannelStopAcquisition = 0x1040; /// R/W not sure
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const uint32_t RCCR2SmoothingFactor = 0x1054; /// R/W Trigger Filter smoothing, triggerSmoothingFactor
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const uint32_t InputRiseTime = 0x1058; /// R/W OK
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const uint32_t TrapezoidRiseTime = 0x105C; /// R/W OK
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const uint32_t TrapezoidFlatTop = 0x1060; /// R/W OK
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const uint32_t PeakingTime = 0x1064; /// R/W OK
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const uint32_t DecayTime = 0x1068; /// R/W OK
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const uint32_t TriggerThreshold = 0x106C; /// R/W OK
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const uint32_t RiseTimeValidationWindow = 0x1070; /// R/W OK
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const uint32_t TriggerHoldOffWidth = 0x1074; /// R/W OK
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const uint32_t PeakHoldOff = 0x1078; /// R/W OK
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const uint32_t ShapedTriggerWidth = 0x1084; /// R/W not sure
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const uint32_t DPPAlgorithmControl2_G = 0x10A0; /// R/W OK
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const uint32_t FineGain = 0x10C4; /// R/W OK
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}
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namespace PSD {
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const uint32_t CFDSetting = 0x103C; /// R/W
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const uint32_t ForcedDataFlush = 0x1040; /// W
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const uint32_t ChargeZeroSuppressionThreshold = 0x1044; /// R/W
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const uint32_t ShortGateWidth = 0x1054; /// R/W
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const uint32_t LongGateWidth = 0x1058; /// R/W
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const uint32_t GateOffset = 0x105C; /// R/W
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const uint32_t TriggerThreshold = 0x1060; /// R/W
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const uint32_t FixedBaseline = 0x1064; /// R/W
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const uint32_t TriggerLatency = 0x106C; /// R/W
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const uint32_t ShapedTriggerWidth = 0x1070; /// R/W
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const uint32_t TriggerHoldOffWidth = 0x1074; /// R/W
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const uint32_t ThresholdForPSDCut = 0x1078; /// R/W
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const uint32_t PurGapThreshold = 0x107C; /// R/W
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const uint32_t DPPAlgorithmControl2_G = 0x1084; /// R/W
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const uint32_t EarlyBaselineFreeze = 0x10D8; /// R/W
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}
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}
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}
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/// This provides an alternative way for control
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namespace Setting{
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enum PHA{
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/// board setting
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AutoDataFlush_board_bool,
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DecimateWaveForm_board_bool,
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TriggerPropapation_board_bool,
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DualTrace_board_bool,
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AnalogProbe1_board_2bit,
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AnalogProbe2_board_2bit,
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WavefromRecording_board_bool,
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EnableExtra2Word_board_bool,
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EnergyRecording_board_bool,
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VirtualProbe_board_4bit,
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/// DPP Algorithm Control 1
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TrapazoidRescaling_5bit,
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WaveformDecimation_2bit,
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WaveformDecimationGain_2bit,
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PeakSampling_2bit,
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PulsePolarity_bool,
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TriggerMode_2bit,
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BaselineSampling_3bit,
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DisableSelfTrigger_bool,
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RolloverFlag_bool,
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PileupFlag_bool,
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/// DPP Algorithm Control 2
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LocalShapedTrigger_bool,
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LocalShapedTriggerMode_2bit,
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LocalTriggerValidation_bool,
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LocalTriggerValidationMode_2bit,
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Extra2WordOption_3bit,
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VetoSource_2bit,
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TriggerCounterRateStep_2bit,
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BaselineCalculationWhenACQOFF_bool,
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TagCorrelatedEvents_bool,
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BaselineRestoreOptimization_bool,
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///ACQ control
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StartStopMode_2bit,
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StartStopACQ_bool,
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PLLClockSource_bool,
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VetoInForTRGOUT_bool,
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/// Registers
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RecordLength_G_ns,
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PreTriggerLength_ns,
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InputDynamicRange_bool,
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DCOffset_precentage,
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VetoWidth_ns,
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EventPreAggregate_G_max1023,
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AggregateOrganization_board_3bit,
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MaxAggregatePreBlockTransfer_board_10bit,
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TriggerThreshold_LSD,
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TriggerHoldOffWidth_ns,
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TriggerSmoothingFactor_5bit,
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TriggerOutputWidth_ns,
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InputRiseTime_ns,
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TrapezoidRiseTime_ns,
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TrapezoidFlatTop_ns,
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DecayTime_ns,
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PeakingTime_ns,
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PeakingHoldOff_ns,
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EnergyFineGain_16bit,
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RiseTimeValidationWindow_ns
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};
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}
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#endif
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