rtang/SOLARIS_QT6_DAQ
1
0
Fork 0
Code Issues Pull Requests Projects Releases 1 Wiki Activity
SOLARIS_QT6_DAQ/DigiParameters.h

1181 lines
80 KiB
C
Raw Normal View History

added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
#ifndef DIGITIZER_PARAMETER_H
#define DIGITIZER_PARAMETER_H
#include <cstdlib>
add settings in digitizer class
2023-02-23 12:24:39 -05:00
#include <string>
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
#include <vector>
fixed using old firmware with new libraries
2023-10-26 17:03:23 -04:00
#define MIN_VERSION_GROUP 2022122300
add the make file in Aux, small change for Ubuntu 23.04
2024-04-11 19:29:23 -04:00
enum ANSTYPE {INTEGER, FLOAT, COMBOX, STR, BYTE, BINARY, NONE};
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
enum TYPE {CH, DIG, LVDS, VGA, GROUP};
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
enum RW { ReadOnly, WriteOnly, ReadWrite};
//^==================== Register Class
class Reg {
private:
std::string name;
add settings in digitizer class
2023-02-23 12:24:39 -05:00
std::string value;
added save and load settings in text file
2023-02-22 20:07:39 -05:00
TYPE type;
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
RW readWrite; // true for read/write, false for read-only
added save and load settings in text file
2023-02-22 20:07:39 -05:00
bool isCmd;
add more data in Reg class
2023-02-24 19:21:27 -05:00
ANSTYPE ansType;
std::string answerUnit;
std::vector<std::pair<std::string, std::string>> answer;
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
public:
add settings in digitizer class
2023-02-23 12:24:39 -05:00
Reg(){
add more data in Reg class
2023-02-24 19:21:27 -05:00
name = "";
readWrite = RW::ReadWrite;
type = TYPE::CH;
isCmd = false;
value = "";
add the make file in Aux, small change for Ubuntu 23.04
2024-04-11 19:29:23 -04:00
ansType = ANSTYPE::COMBOX;
add more data in Reg class
2023-02-24 19:21:27 -05:00
answerUnit = "";
answer.clear();
add settings in digitizer class
2023-02-23 12:24:39 -05:00
}
add more data in Reg class
2023-02-24 19:21:27 -05:00
Reg(std::string para, RW readwrite,
TYPE type = TYPE::CH,
std::vector<std::pair<std::string,std::string>> answer = {},
add the make file in Aux, small change for Ubuntu 23.04
2024-04-11 19:29:23 -04:00
ANSTYPE ansType = ANSTYPE::COMBOX,
add more data in Reg class
2023-02-24 19:21:27 -05:00
std::string ansUnit = "",
bool isCmd = false){
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
this->name = para;
this->readWrite = readwrite;
added save and load settings in text file
2023-02-22 20:07:39 -05:00
this->type = type;
this->isCmd = isCmd;
add settings in digitizer class
2023-02-23 12:24:39 -05:00
this->value = "";
add more data in Reg class
2023-02-24 19:21:27 -05:00
this->ansType = ansType;
this->answer = answer;
this->answerUnit = ansUnit;
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
}
~Reg(){};
add the make file in Aux, small change for Ubuntu 23.04
2024-04-11 19:29:23 -04:00
void SetValue(std::string sv) { value = sv;}
add settings in digitizer class
2023-02-23 12:24:39 -05:00
std::string GetValue() const { return value;}
add more data in Reg class
2023-02-24 19:21:27 -05:00
RW ReadWrite() const {return readWrite;}
TYPE GetType() const {return type;}
ANSTYPE GetAnswerType() const {return ansType;}
std::string GetUnit() const {return answerUnit;}
std::vector<std::pair<std::string,std::string>> GetAnswers() const {return answer;}
add settings in digitizer class
2023-02-23 12:24:39 -05:00
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
std::string GetPara() const {return name;}
added save and load settings in text file
2023-02-22 20:07:39 -05:00
std::string GetFullPara(int ch_index = -1) const {
switch (type){
case TYPE::DIG:{
if( isCmd){
return "/cmd/" + name;
}else{
return "/par/" + name;
}
}; break;
case TYPE::CH:{
std::string haha = "/par/";
if( isCmd ){
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
haha = "/cmd/"; // for SendChSWTrigger, not in GUI
added save and load settings in text file
2023-02-22 20:07:39 -05:00
}
if( ch_index == -1 ){
return "/ch/0..63" + haha + name;
}else{
return "/ch/" + std::to_string(ch_index) + haha + name;
}
}; break;
case TYPE::LVDS:{
if( ch_index == -1 ){
return "/lvds/0..3/par/" + name;
}else{
return "/lvds/" + std::to_string(ch_index) + "/par/"+ name;
}
}; break;
case TYPE::VGA: {
if( ch_index == -1 ){
return "/vga/0..3/par/" + name;
}else{
return "/vga/" + std::to_string(ch_index) + "/par/"+ name;
}
}; break;
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
case TYPE::GROUP:{
if( ch_index == -1 ){
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
return "/group/0..15/par/" + name;
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
}else{
return "/group/" + std::to_string(ch_index) + "/par/" + name;
}
break;
}
added save and load settings in text file
2023-02-22 20:07:39 -05:00
default:
return "invalid"; break;
}
}
add more data in Reg class
2023-02-24 19:21:27 -05:00
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
operator std::string () const {return name;} // this allow Reg kaka("XYZ", true); std::string haha = kaka;
};
//^==================== Some digitizer parameters
complete the digiSetting Panel
2023-03-14 16:17:22 -04:00
namespace PHA{
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
const unsigned short TraceStep = 8;
namespace DIG{
///============== read only
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg CupVer ("CupVer", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg FPGA_firmwareVersion ("FPGA_FwVer", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg FirmwareType ("FwType", RW::ReadOnly, TYPE::DIG, {{"DPP_PHA", ""}, {"DPP_ZLE", ""}, {"DPP_PSD", ""}, {"DPP_DAW", ""}, {"DPP_OPEN", ""}, {"Scope", ""}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg ModelCode ("ModelCode", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg PBCode ("PBCode", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg ModelName ("ModelName", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg FromFactor ("FormFactor", RW::ReadOnly, TYPE::DIG, {{"0", "VME"}, {"1", "VME64X"}, {"2", "DT"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg FamilyCode ("FamilyCode", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER);
const Reg SerialNumber ("SerialNum", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER);
const Reg PCBrev_MB ("PCBrev_MB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER);
const Reg PCBrev_PB ("PCBrev_PB", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER);
const Reg DPP_License ("License", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg DPP_LicenseStatus ("LicenseStatus", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg DPP_LicenseRemainingTime ("LicenseRemainingTime", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER);
const Reg NumberOfChannel ("NumCh", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER);
const Reg ADC_bit ("ADC_Nbit", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "sec");
const Reg ADC_SampleRate ("ADC_SamplRate", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "MS/s");
const Reg InputDynamicRange ("InputRange", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "Vpp");
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg InputType ("InputType", RW::ReadOnly, TYPE::DIG, {{"0","Singled ended"}, {"1", "Differential"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg InputImpedance ("Zin", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "Ohm");
const Reg IPAddress ("IPAddress", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg NetMask ("Netmask", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
const Reg Gateway ("Gateway", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR);
add more ANSTYPE for 64-byte or binary
2023-03-14 16:40:54 -04:00
const Reg LED_status ("LedStatus", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::BINARY, "byte");
const Reg ACQ_status ("AcquisitionStatus", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::BINARY, "byte");
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg MaxRawDataSize ("MaxRawDataSize", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::STR, "byte");
const Reg TempSensAirIn ("TempSensAirIn", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensAirOut ("TempSensAirOut", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensCore ("TempSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensFirstADC ("TempSensFirstADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensLastADC ("TempSensLastADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensHottestADC ("TempSensHottestADC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC0 ("TempSensADC0", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC1 ("TempSensADC1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC2 ("TempSensADC2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC3 ("TempSensADC3", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC4 ("TempSensADC4", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC5 ("TempSensADC5", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC6 ("TempSensADC6", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg TempSensADC7 ("TempSensADC7", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
added save and load settings in text file
2023-02-22 20:07:39 -05:00
const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7};
UpdateScalar also update digiSettings status, if exist and visible
2023-04-14 14:10:02 -04:00
const std::vector<Reg> TempSensOthers = {TempSensAirIn,TempSensAirOut,TempSensCore,TempSensFirstADC,TempSensLastADC,TempSensHottestADC};
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg TempSensDCDC ("TempSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "C");
const Reg VInSensDCDC ("VInSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "V");
const Reg VOutSensDCDC ("VOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "V");
const Reg IOutSensDCDC ("IOutSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "Amp");
const Reg FreqSensCore ("FreqSensCore", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "Hz");
const Reg DutyCycleSensDCDC ("DutyCycleSensDCDC", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "%");
const Reg SpeedSensFan1 ("SpeedSensFan1", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "rpm");
const Reg SpeedSensFan2 ("SpeedSensFan2", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::INTEGER, "rpm");
add more ANSTYPE for 64-byte or binary
2023-03-14 16:40:54 -04:00
const Reg ErrorFlags ("ErrorFlags", RW::ReadOnly, TYPE::DIG, {}, ANSTYPE::BINARY, "byte");
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg BoardReady ("BoardReady", RW::ReadOnly, TYPE::DIG, {{"True", "No Error"}, {"False", "Error"}});
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
const Reg SPFLinkPresence ("SPFLinkPresence", RW::ReadOnly, TYPE::DIG, {{"True", "Inserted"}, {"False", "Disconnected"}});
const Reg SPFLinkActive ("SPFLinkActive", RW::ReadOnly, TYPE::DIG, {{"True", "Active"}, {"False", "Deactive"}});
const Reg SPFLinkProtocol ("SPFLinkProtocal", RW::ReadOnly, TYPE::DIG, {{"Eth1G", "1 GB/s"}, {"Eth10G", "10 GB/s"}, {"CONET2", "Conet2"}});
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
///============= read write
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg ClockSource ("ClockSource", RW::ReadWrite, TYPE::DIG, {{"Internal", "Internal Clock 62.5 MHz"},
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
{"FPClkIn", "Front Panel Clock Input"}});
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg IO_Level ("IOlevel", RW::ReadWrite, TYPE::DIG, {{"NIM", "NIM (0=0V, 1=-0.8V) "}, {"TTL", "TTL (0=0V, 1=3.3V)"}});
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
const Reg StartSource ("StartSource", RW::ReadWrite, TYPE::DIG, {{"EncodedClkIn", "CLK-IN/SYNC"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"SINlevel", "S-IN Level"},
{"SINedge", "S-IN Edge"},
{"SWcmd", "Software"},
small improvement on digiSettignPanel
2023-03-14 17:35:27 -04:00
{"LVDS", "LVDS"}}, ANSTYPE::STR);
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg GlobalTriggerSource ("GlobalTriggerSource", RW::ReadWrite, TYPE::DIG,{{"TrgIn", "TRG-IN" },
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
{"SwTrg", "Software" },
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"GPIO", "GPIO" },
{"TestPulse", "Test Pulse" },
small improvement on digiSettignPanel
2023-03-14 17:35:27 -04:00
{"LVDS", "LVDS"}}, ANSTYPE::STR);
add more data in Reg class
2023-02-24 19:21:27 -05:00
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
const Reg BusyInSource ("BusyInSource", RW::ReadWrite, TYPE::DIG, {{"Disabled","Disabled"},
{"SIN", "SIN"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"GPIO", "GPIO"},
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
{"LVDS", "LVDS"}});
added save and load settings in text file
2023-02-22 20:07:39 -05:00
//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg EnableClockOutFrontPanel ("EnClockOutFP", RW::ReadWrite, TYPE::DIG, {{"True", "Enable"}, {"False", "Disabled"}});
const Reg TrgOutMode ("TrgOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
{"TRGIN", "TRG-IN"},
{"SwTrg", "Software Trigger"},
{"LVDS", "LVDS"},
completed ITL setting UI
2023-09-18 19:16:28 -04:00
{"ITLA", "ITL-A"},
{"ITLB", "ITL-B"},
{"ITLA_AND_ITLB", "ITL-A & B"},
{"ITLA_OR_ITLB", "ITL-A || B"},
{"EncodedClkIn", "Encoded CLK-IN"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"Run", "Run Signal"},
{"RefClk", "Reference Clock"},
{"TestPulse", "Test Pulse"},
{"Busy", "Busy Signal"},
{"Fixed0", "0-level"},
{"Fixed1", "1-level"},
{"SyncIn", "SyncIn Signal"},
{"SIN", "S-IN Signal"},
{"GPIO", "GPIO Signal"},
add ITL-AB and LVDS setting parameters, re-structure the digiSetting UI, leave space for LVDS and ITL settings
2023-09-18 17:05:13 -04:00
{"AcceptTrg", "Acceped Trigger Signal"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"TrgClk", "Trigger Clock"}});
const Reg GPIOMode ("GPIOMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
{"TRGIN", "TRG-IN"},
{"P0", "Back Plane"},
completed ITL setting UI
2023-09-18 19:16:28 -04:00
{"SIN", "S-IN Signal"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"LVDS", "LVDS Trigger"},
completed ITL setting UI
2023-09-18 19:16:28 -04:00
{"ITLA", "ITL-A"},
{"ITLB", "ITL-B"},
{"ITLA_AND_ITLB", "ITL-A & B"},
{"ITLA_OR_ITLB", "ITL-A || B"},
{"EncodedClkIn", "Encoded CLK-IN"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"SwTrg", "Software Trigger"},
{"Run", "Run Signal"},
{"RefClk", "Referece Clock"},
{"TestPulse", "Test Pulse"},
{"Busy", "Busy Signal"},
{"Fixed0", "0-Level"},
{"Fixed1", "1-Level"}});
const Reg SyncOutMode ("SyncOutMode", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
{"SyncIn", "Sync-In Signal"},
{"TestPulse", "Test Pulse"},
{"IntClk", "Internal Clock 62.5MHz"},
{"Run", "Run Signal"} });
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
const Reg BoardVetoSource ("BoardVetoSource", RW::ReadWrite, TYPE::DIG, {{"Disabled", "Disabled"},
{"SIN", "S-IN"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"LVDS", "LVDS"},
{"GPIO", "GPIO"},
completed ITL setting UI
2023-09-18 19:16:28 -04:00
{"P0", "Back Plane"},
{"EncodedClkIn", "Encoded CLK-IN"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg BoardVetoWidth ("BoardVetoWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"34359738360", ""}, {"1", ""}}, ANSTYPE::INTEGER, "ns");
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
const Reg BoardVetoPolarity ("BoardVetoPolarity", RW::ReadWrite, TYPE::DIG, {{"ActiveHigh", "High"}, {"ActiveLow", "Low"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg RunDelay ("RunDelay", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"524280", ""}, {"1", ""}}, ANSTYPE::INTEGER, "ns");
snapshot, in progress of digiSettingPanel
2023-02-27 15:23:28 -05:00
const Reg EnableAutoDisarmACQ ("EnAutoDisarmAcq", RW::ReadWrite, TYPE::DIG, {{"True", "Enabled"}, {"False", "Disabled"}});
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg EnableDataReduction ("EnDataReduction", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
const Reg EnableStatisticEvents ("EnStatEvents", RW::ReadWrite, TYPE::DIG, {{"False", "Disabled"}, {"True", "Enabled"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg VolatileClockOutDelay ("VolatileClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}, {"74.074", ""}}, ANSTYPE::FLOAT, "ps");
const Reg PermanentClockOutDelay ("PermanentClockOutDelay", RW::ReadWrite, TYPE::DIG, {{"-18888.888", ""}, {"18888.888", ""}, {"74.074", ""}}, ANSTYPE::FLOAT, "ps");
const Reg TestPulsePeriod ("TestPulsePeriod", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}, {"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg TestPulseWidth ("TestPulseWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"34359738360", ""}, {"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg TestPulseLowLevel ("TestPulseLowLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}, {"1", ""}}, ANSTYPE::INTEGER, "ns");
const Reg TestPulseHighLevel ("TestPulseHighLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""},{"65535", ""}, {"1", ""}}, ANSTYPE::INTEGER, "ns");
add more ANSTYPE for 64-byte or binary
2023-03-14 16:40:54 -04:00
const Reg ErrorFlagMask ("ErrorFlagMask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BINARY);
const Reg ErrorFlagDataMask ("ErrorFlagDataMask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BINARY);
added LVDS and DAC settings, some bugs fixed
2023-09-19 19:19:07 -04:00
const Reg DACoutMode ("DACoutMode", RW::ReadWrite, TYPE::DIG, {{"Static", "DAC static level"},
{"ChInput", "From Channel"},
{"ChSum", "Sum of all Channels"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"OverThrSum", "Number of Channels triggered"},
added LVDS and DAC settings, some bugs fixed
2023-09-19 19:19:07 -04:00
{"Ramp", "14-bit counter"},
{"Sin5MHz", "5 MHz Sin wave Vpp = 2V"},
{"Square", "Test Pulse"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg DACoutStaticLevel ("DACoutStaticLevel", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"16383", ""}, {"1",""}}, ANSTYPE::INTEGER, "units");
const Reg DACoutChSelect ("DACoutChSelect", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"64", ""}, {"1",""}}, ANSTYPE::INTEGER);
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg EnableOffsetCalibration ("EnOffsetCalibration", RW::ReadWrite, TYPE::DIG, {{"True", "Applied Cali."}, {"False", "No Cali."}});
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
add ITL-AB and LVDS setting parameters, re-structure the digiSetting UI, leave space for LVDS and ITL settings
2023-09-18 17:05:13 -04:00
const Reg ITLAMainLogic ("ITLAMainLogic", RW::ReadWrite, TYPE::DIG, {{"OR", "OR"},{"AND", "AND"}, {"Majority", "Majority"}});
const Reg ITLAMajorityLev ("ITLAMajorityLev", RW::ReadWrite, TYPE::DIG, {{"1", ""},{"63", ""}, {"1", ""}}, ANSTYPE::INTEGER);
const Reg ITLAPairLogic ("ITLAPairLogic", RW::ReadWrite, TYPE::DIG, {{"OR", "OR"},{"AND", "AND"}, {"NONE", "NONE"}});
const Reg ITLAPolarity ("ITLAPolarity", RW::ReadWrite, TYPE::DIG, {{"Direct", "Direct"},{"Inverted", "Inverted"}});
const Reg ITLAMask ("ITLAMask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BYTE, "64-bit");
const Reg ITLAGateWidth ("ITLAGateWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"524280", ""}, {"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg ITLBMainLogic ("ITLBMainLogic", RW::ReadWrite, TYPE::DIG, {{"OR", "OR"},{"AND", "AND"}, {"Majority", "Majority"}});
const Reg ITLBMajorityLev ("ITLBMajorityLev", RW::ReadWrite, TYPE::DIG, {{"1", ""},{"63", ""}, {"1", ""}}, ANSTYPE::INTEGER);
const Reg ITLBPairLogic ("ITLBPairLogic", RW::ReadWrite, TYPE::DIG, {{"OR", "OR"},{"AND", "AND"}, {"NONE", "NONE"}});
const Reg ITLBPolarity ("ITLBPolarity", RW::ReadWrite, TYPE::DIG, {{"Direct", "Direct"},{"Inverted", "Inverted"}});
const Reg ITLBMask ("ITLBMask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BYTE, "64-bit");
const Reg ITLBGateWidth ("ITLBGateWidth", RW::ReadWrite, TYPE::DIG, {{"0", ""}, {"524280", ""}, {"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg LVDSIOReg ("LVDSIOReg", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::STR);
//const Reg LVDSTrgMask ("lvdstrgmask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BYTE, "64-bit");
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
/// ========== command
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg Reset ("Reset", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const Reg ClearData ("ClearData", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // clear memory, setting not affected
const Reg ArmACQ ("ArmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const Reg DisarmACQ ("DisarmAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
const Reg SoftwareStartACQ ("SwStartAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only when SwStart in StartSource
const Reg SoftwareStopACQ ("SwStopAcquisition", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // stop ACQ, whatever start source
const Reg SendSoftwareTrigger ("SendSWTrigger", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); // only work when Swtrg in the GlobalTriggerSource
const Reg ReloadCalibration ("ReloadCalibration", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true);
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
const Reg Reboot ("Reboot", RW::WriteOnly, TYPE::DIG, {}, ANSTYPE::NONE, "", true); //^ not implemented
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
const std::vector<Reg> AllSettings = {
CupVer ,
FPGA_firmwareVersion ,
FirmwareType ,
ModelCode ,
PBCode ,
ModelName ,
FromFactor ,
FamilyCode ,
SerialNumber ,
PCBrev_MB ,
PCBrev_PB ,
DPP_License ,
DPP_LicenseStatus ,
DPP_LicenseRemainingTime ,
NumberOfChannel ,
snapshot of digiSettingsPanel
2023-02-23 16:08:47 -05:00
ADC_bit ,
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
ADC_SampleRate ,
InputDynamicRange ,
InputType ,
InputImpedance ,
IPAddress ,
NetMask ,
Gateway ,
LED_status ,
ACQ_status ,
MaxRawDataSize ,
TempSensAirIn ,
TempSensAirOut ,
TempSensCore ,
TempSensFirstADC ,
TempSensLastADC ,
TempSensHottestADC ,
TempSensADC0 ,
TempSensADC1 ,
TempSensADC2 ,
TempSensADC3 ,
TempSensADC4 ,
TempSensADC5 ,
TempSensADC6 ,
TempSensADC7 ,
TempSensDCDC ,
VInSensDCDC ,
VOutSensDCDC ,
IOutSensDCDC ,
FreqSensCore ,
DutyCycleSensDCDC ,
SpeedSensFan1 ,
SpeedSensFan2 ,
ErrorFlags ,
BoardReady ,
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
// SPFLinkPresence ,
// SPFLinkActive ,
// SPFLinkProtocol ,
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
ClockSource ,
IO_Level ,
StartSource ,
GlobalTriggerSource ,
BusyInSource ,
added save and load settings in text file
2023-02-22 20:07:39 -05:00
//EnableClockOutBackplane ,
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
EnableClockOutFrontPanel ,
TrgOutMode ,
GPIOMode ,
SyncOutMode ,
BoardVetoSource ,
BoardVetoWidth ,
BoardVetoPolarity ,
RunDelay ,
EnableAutoDisarmACQ ,
EnableDataReduction ,
EnableStatisticEvents ,
VolatileClockOutDelay ,
PermanentClockOutDelay ,
TestPulsePeriod ,
TestPulseWidth ,
TestPulseLowLevel ,
TestPulseHighLevel ,
ErrorFlagMask ,
ErrorFlagDataMask ,
DACoutMode ,
DACoutStaticLevel ,
DACoutChSelect ,
add ITL-AB and LVDS setting parameters, re-structure the digiSetting UI, leave space for LVDS and ITL settings
2023-09-18 17:05:13 -04:00
EnableOffsetCalibration ,
ITLAMainLogic ,
ITLAMajorityLev ,
ITLAPairLogic ,
ITLAPolarity ,
ITLAMask ,
ITLAGateWidth ,
ITLBMainLogic ,
ITLBMajorityLev ,
ITLBPairLogic ,
ITLBPolarity ,
ITLBMask ,
ITLBGateWidth ,
LVDSIOReg
//LVDSTrgMask
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
};
}
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
namespace GROUP{
improved the Input Delay
2023-10-26 16:37:29 -04:00
const Reg InputDelay ("InputDelay", RW::ReadWrite, TYPE::GROUP, {{"0",""}, {"32768", ""}, {"8", ""}}, ANSTYPE::INTEGER, "ns");
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
}
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
namespace VGA{
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg VGAGain ("VGAGain", RW::ReadWrite, TYPE::VGA, {{"0", ""},{"40", ""}, {"0.5",""}}, ANSTYPE::INTEGER, "dB"); // VX2745 only
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
}
add ITL-AB and LVDS setting parameters, re-structure the digiSetting UI, leave space for LVDS and ITL settings
2023-09-18 17:05:13 -04:00
namespace LVDS{
const Reg LVDSMode ("LVDSMode", RW::ReadWrite, TYPE::LVDS, {{"SelfTriggers", "Self-Trigger"},
{"Sync", "Sync"},
{"IORegister", "IORegister"}});
const Reg LVDSDirection ("LVDSDirection", RW::ReadWrite, TYPE::LVDS, {{"Input", "Input"},
{"Output", "Output"}});
const std::vector<Reg> AllSettings = {
LVDSMode ,
LVDSDirection
};
}
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
namespace CH{
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
/// ========= command
const Reg SendChSWTrigger ("SendChSWrigger", RW::WriteOnly, TYPE::CH, {}, ANSTYPE::NONE, "", true);
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
/// ========= red only
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg SelfTrgRate ("SelfTrgRate", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::INTEGER, "Hz");
const Reg ChannelStatus ("ChStatus", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
const Reg GainFactor ("GainFactor", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::FLOAT);
const Reg ADCToVolts ("ADCToVolts", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::FLOAT);
const Reg Energy_Nbit ("Energy_Nbit", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
const Reg ChannelRealtime ("ChRealtimeMonitor", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR); // when called, update DeadTime, TriggerCount, SaveCount, and WaveCount
const Reg ChannelDeadtime ("ChDeadtimeMonitor", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
const Reg ChannelTriggerCount ("ChTriggerCnt", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
const Reg ChannelSavedCount ("ChSavedEventCnt", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
const Reg ChannelWaveCount ("ChWaveCnt", RW::ReadOnly, TYPE::CH, {}, ANSTYPE::STR);
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
/// ======= read write
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
//^ not impletemented
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
const Reg SelfTriggerWidth ("SelfTriggerWidth", RW::ReadWrite, TYPE::CH, {{"0", ""},{"6000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns"); // not sure the max
const Reg SignalOffset ("SignalOffset", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "uV"); // not sure the max
update the DigiParameters.h and Digitizer Class for latest PHA firmware. new parameters are not implemented. Still supporting old firmware
2023-10-16 13:27:40 -04:00
//^ impletemented
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg ChannelEnable ("ChEnable", RW::ReadWrite, TYPE::CH, {{"True", "Enabled"}, {"False", "Disabled"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg DC_Offset ("DCOffset", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"100", ""}, {"1",""}}, ANSTYPE::INTEGER, "%");
const Reg TriggerThreshold ("TriggerThr", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8191", ""}, {"1",""}}, ANSTYPE::INTEGER);
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg Polarity ("PulsePolarity", RW::ReadWrite, TYPE::CH, {{"Positive", "Pos. +"},{"Negative", "Neg. -"}});
const Reg WaveDataSource ("WaveDataSource", RW::ReadWrite, TYPE::CH, {{"ADC_DATA", "Input ADC"},
{"ADC_TEST_TOGGLE", "ADC produces TOGGLE signal"},
{"ADC_TEST_RAMP", "ADC produces RAMP signal"},
{"ADC_TEST_SIN", "ADC produce SIN signal"},
{"Ramp", "Ramp generator"},
{"SquareWave", "Test Pusle (Square Wave)"} });
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg RecordLength ("ChRecordLengthT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"64800", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
const Reg PreTrigger ("ChPreTriggerT", RW::ReadWrite, TYPE::CH, {{"32", ""}, {"32000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg WaveSaving ("WaveSaving", RW::ReadWrite, TYPE::CH, {{"Always", "Always"}, {"OnRequest", "On Request"}});
except VGA setting, all settings done
2023-03-02 15:00:59 -05:00
const Reg WaveResolution ("WaveResolution", RW::ReadWrite, TYPE::CH, {{"RES8", " 8 ns"},
{"RES16","16 ns"},
{"RES32","32 ns"},
{"RES64","64 ns"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg TimeFilterRiseTime ("TimeFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"2000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
const Reg EnergyFilterRiseTime ("EnergyFilterRiseTimeT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"13000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
const Reg EnergyFilterFlatTop ("EnergyFilterFlatTopT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"3000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
const Reg EnergyFilterPoleZero ("EnergyFilterPoleZeroT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"524000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
All channel setting tab can show signal channel
2023-03-13 19:23:14 -04:00
const Reg EnergyFilterPeakingPosition ("EnergyFilterPeakingPosition", RW::ReadWrite, TYPE::CH, {{"10", ""},{"90", ""}, {"1",""}}, ANSTYPE::INTEGER, "%");
improving digiSettingPanel
2023-02-28 13:28:30 -05:00
const Reg EnergyFilterPeakingAvg ("EnergyFilterPeakingAvg", RW::ReadWrite, TYPE::CH, {{"OneShot", "1 sample"},
{"LowAVG", "4 samples"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"MediumAVG", "16 samples"},
{"HighAVG", "64 samples"}});
improving digiSettingPanel
2023-02-28 13:28:30 -05:00
const Reg EnergyFilterBaselineAvg ("EnergyFilterBaselineAvg", RW::ReadWrite, TYPE::CH, {{"Fixed", "0 sample"},
{"VeryLow", "16 samples"},
{"Low", "64 samples"},
{"MediumLow", "256 samples"},
{"Medium", "1024 samples"},
{"MediumHigh","4096 samples"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"High", "16384 samples"}});
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg EnergyFilterBaselineGuard ("EnergyFilterBaselineGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
const Reg EnergyFilterFineGain ("EnergyFilterFineGain", RW::ReadWrite, TYPE::CH, {{"0", ""},{"10", ""}, {"0.001",""}}, ANSTYPE::FLOAT);
const Reg EnergyFilterPileUpGuard ("EnergyFilterPileUpGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"64000", ""}, {"8",""}}, ANSTYPE::INTEGER, "ns");
except VGA setting, all settings done
2023-03-02 15:00:59 -05:00
const Reg EnergyFilterLowFreqFilter ("EnergyFilterLFLimitation", RW::ReadWrite, TYPE::CH, {{"Off", "Disabled"}, {"On", "Enabled"}});
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
{"TimeFilter", "Time Filter"},
{"EnergyFilter", "Trapazoid"},
{"EnergyFilterBase", "Trap. Baseline"},
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
{"TimeFilter", "Time Filter"},
{"EnergyFilter", "Trapazoid"},
{"EnergyFilterBase", "Trap. Baseline"},
{"EnergyFilterMinusBaseline", "Trap. - Baseline"}});
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"TimeFilterArmed", "Time Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"EnergyFilterBaselineFreeze", "Trap. basline Freeze"},
{"EnergyFilterPeaking", "Peaking"},
{"EnergyFilterPeakReady", "Peak Ready"},
{"EnergyFilterPileUpGuard", "Pile-up Guard"},
{"EventPileUp", "Event Pile Up"},
{"ADCSaturation", "ADC Saturate"},
{"ADCSaturationProtection", "ADC Sat. Protection"},
{"PostSaturationEvent", "Post Sat. Event"},
{"EnergylterSaturation", "Trap. Saturate"},
{"AcquisitionInhibit", "ACQ Inhibit"} });
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1};
const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3};
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg EventTriggerSource ("EventTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
{"TRGIN", "TRG-IN"},
{"SWTrigger", "Software Trigger"},
{"ChSelfTrigger", "Channel Self-Trigger"},
{"Ch64Trigger", "Channel 64-Trigger"},
{"Disabled", "Disabled"}});
add more ANSTYPE for 64-byte or binary
2023-03-14 16:40:54 -04:00
const Reg ChannelsTriggerMask ("ChannelsTriggerMask", RW::ReadWrite, TYPE::CH, {}, ANSTYPE::BYTE, "64-bit" );
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg ChannelVetoSource ("ChannelVetoSource", RW::ReadWrite, TYPE::CH, {{"BoardVeto", "Board Veto"},
{"ADCOverSaturation", "ADC Over Saturation"},
finished all settings. next channel status, and spinbox step
2023-03-02 18:18:02 -05:00
{"ADCUnderSaturation", "ADC Under Saturation"},
{"Disabled", "Disabled"}});
add more data in Reg class
2023-02-24 19:21:27 -05:00
const Reg WaveTriggerSource ("WaveTriggerSource", RW::ReadWrite, TYPE::CH, {{"GlobalTriggerSource", "Global Trigger Source"},
{"TRGIN", "TRG-IN"},
{"ExternalInhibit", "External Inhibit"},
{"ADCUnderSaturation", "ADC Under Saturation"},
{"ADCOverSaturation", "ADC Over Saturation"},
{"SWTrigger", "Software Trigger"},
{"ChSelfTrigger", "Channel Self-Trigger"},
{"Ch64Trigger", "Channel 64-Trigger"},
{"Disabled", "Disabled"}});
const Reg EventSelector ("EventSelector", RW::ReadWrite, TYPE::CH, {{"All", "All"},
{"Pileup", "Pile up"},
{"EnergySkim", "Energy Skim"}});
const Reg WaveSelector ("WaveSelector", RW::ReadWrite, TYPE::CH, {{"All", "All wave"},
{"Pileup", "Only Pile up"},
{"EnergySkim", "Only in Energy Skim Range"}});
finished all settings. next channel status, and spinbox step
2023-03-02 18:18:02 -05:00
const Reg CoincidenceMask ("CoincidenceMask", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"Ch64Trigger", "Channel 64-Trigger"},
{"TRGIN", "TRG-IN"},
{"GlobalTriggerSource", "Global Trigger"},
{"ITLA", "ITLA"},
{"ITLB", "ITLB"}});
finished all settings. next channel status, and spinbox step
2023-03-02 18:18:02 -05:00
const Reg AntiCoincidenceMask ("AntiCoincidenceMask", RW::ReadWrite, TYPE::CH,{{"Disabled", "Disabled"},
add more data in Reg class
2023-02-24 19:21:27 -05:00
{"Ch64Trigger", "Channel 64-Trigger"},
{"TRGIN", "TRG-IN"},
{"GlobalTriggerSource", "Global Trigger"},
{"ITLA", "ITLA"},
{"ITLB", "ITLB"}});
small improvement on digiSettignPanel
2023-03-14 17:35:27 -04:00
const Reg CoincidenceLength ("CoincidenceLengthT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"524280", ""}, {"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg CoincidenceLengthSample ("CoincidenceLengthS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"65535", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
finsiah the low level settings
2023-03-13 16:51:11 -04:00
const Reg ADCVetoWidth ("ADCVetoWidth", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"524280", ""}, {"1", ""}}, ANSTYPE::INTEGER, "ns");
const Reg EnergySkimLowDiscriminator ("EnergySkimLowDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}, {"1", ""}}, ANSTYPE::INTEGER);
const Reg EnergySkimHighDiscriminator ("EnergySkimHighDiscriminator", RW::ReadWrite, TYPE::CH, {{"0", ""}, {"65534", ""}, {"1", ""}}, ANSTYPE::INTEGER);
const Reg RecordLengthSample ("ChRecordLengthS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"8100", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg PreTriggerSample ("ChPreTriggerS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"4000", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg TimeFilterRiseTimeSample ("TimeFilterRiseTimeS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"250", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg TimeFilterRetriggerGuardSample ("TimeFilterRetriggerGuardS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg EnergyFilterRiseTimeSample ("EnergyFilterRiseTimeS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"1625", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg EnergyFilterFlatTopSample ("EnergyFilterFlatTopS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"375", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg EnergyFilterPoleZeroSample ("EnergyFilterPoleZeroS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"65500", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg EnergyFilterBaselineGuardSample ("EnergyFilterBaselineGuardS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg EnergyFilterPileUpGuardSample ("EnergyFilterPileUpGuardS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""}, {"1", ""}}, ANSTYPE::INTEGER, "sample");
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
add ITL-AB and LVDS setting parameters, re-structure the digiSetting UI, leave space for LVDS and ITL settings
2023-09-18 17:05:13 -04:00
const Reg ITLConnect ("ITLConnect", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},{"ITLA", "ITLA"}, {"ITLB", "ITLB"}});
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
const std::vector<Reg> AllSettings = {
fix ReadData logic problem
2023-09-22 17:57:43 -04:00
SelfTrgRate , // 0
ChannelStatus , // 1
GainFactor , // 2
ADCToVolts , // 3
Energy_Nbit , // 4
ChannelRealtime , // 5
ChannelDeadtime , // 6
ChannelTriggerCount , // 7
ChannelSavedCount , // 8
ChannelWaveCount , // 9
ChannelEnable , // 0
DC_Offset , // 1
TriggerThreshold , // 2
Polarity , // 3
WaveDataSource , // 4
RecordLength , // 5
PreTrigger , // 6
WaveSaving , // 7
WaveResolution , // 8
EventTriggerSource , // 9
ChannelsTriggerMask , // 10
ChannelVetoSource , // 11
WaveTriggerSource , // 12
EventSelector , // 13
WaveSelector , // 14
CoincidenceMask , // 15
AntiCoincidenceMask , // 16
CoincidenceLength , // 17
ADCVetoWidth , // 18
EnergySkimLowDiscriminator , // 19
EnergySkimHighDiscriminator, // 20
ITLConnect , // 21
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
TimeFilterRiseTime ,
TimeFilterRetriggerGuard ,
EnergyFilterRiseTime ,
EnergyFilterFlatTop ,
EnergyFilterPoleZero ,
EnergyFilterBaselineGuard ,
EnergyFilterPileUpGuard ,
EnergyFilterPeakingPosition,
EnergyFilterPeakingAvg ,
EnergyFilterFineGain ,
EnergyFilterLowFreqFilter ,
EnergyFilterBaselineAvg ,
WaveAnalogProbe0 ,
WaveAnalogProbe1 ,
WaveDigitalProbe0 ,
WaveDigitalProbe1 ,
WaveDigitalProbe2 ,
remove settings using Sample in setting file
2023-10-19 09:38:57 -04:00
WaveDigitalProbe3
// CoincidenceLengthSample ,
// RecordLengthSample ,
// PreTriggerSample ,
// TimeFilterRiseTimeSample ,
// TimeFilterRetriggerGuardSample ,
// EnergyFilterRiseTimeSample ,
// EnergyFilterFlatTopSample ,
// EnergyFilterPoleZeroSample ,
// EnergyFilterBaselineGuardSample ,
// EnergyFilterPileUpGuardSample
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
};
}
};
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
namespace PSD{
fix ReadData logic problem
2023-09-22 17:57:43 -04:00
namespace DIG{ // the PSD::DIG are identical to PHA::DIG
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
///============== read only
const Reg CupVer = PHA::DIG::CupVer;
const Reg FPGA_firmwareVersion = PHA::DIG::FPGA_firmwareVersion;
const Reg FirmwareType = PHA::DIG::FirmwareType;
const Reg ModelCode = PHA::DIG::ModelCode;
const Reg PBCode = PHA::DIG::PBCode;
const Reg ModelName = PHA::DIG::ModelName;
const Reg FromFactor = PHA::DIG::FromFactor;
const Reg FamilyCode = PHA::DIG::FamilyCode;
const Reg SerialNumber = PHA::DIG::SerialNumber;
const Reg PCBrev_MB = PHA::DIG::PCBrev_MB;
const Reg PCBrev_PB = PHA::DIG::PCBrev_PB;
const Reg DPP_License = PHA::DIG::DPP_License;
const Reg DPP_LicenseStatus = PHA::DIG::DPP_LicenseStatus;
const Reg DPP_LicenseRemainingTime = PHA::DIG::DPP_LicenseRemainingTime;
const Reg NumberOfChannel = PHA::DIG::NumberOfChannel;
const Reg ADC_bit = PHA::DIG::ADC_bit;
const Reg ADC_SampleRate = PHA::DIG::ADC_SampleRate;
const Reg InputDynamicRange = PHA::DIG::InputDynamicRange;
const Reg InputType = PHA::DIG::InputType;
const Reg InputImpedance = PHA::DIG::InputImpedance;
const Reg IPAddress = PHA::DIG::IPAddress;
const Reg NetMask = PHA::DIG::NetMask;
const Reg Gateway = PHA::DIG::Gateway;
const Reg LED_status = PHA::DIG::LED_status;
const Reg ACQ_status = PHA::DIG::ACQ_status;
const Reg MaxRawDataSize = PHA::DIG::MaxRawDataSize;
const Reg TempSensAirIn = PHA::DIG::TempSensAirIn;
const Reg TempSensAirOut = PHA::DIG::TempSensAirOut;
const Reg TempSensCore = PHA::DIG::TempSensCore;
const Reg TempSensFirstADC = PHA::DIG::TempSensFirstADC;
const Reg TempSensLastADC = PHA::DIG::TempSensLastADC;
const Reg TempSensHottestADC = PHA::DIG::TempSensHottestADC;
const Reg TempSensADC0 = PHA::DIG::TempSensADC0;
const Reg TempSensADC1 = PHA::DIG::TempSensADC1;
const Reg TempSensADC2 = PHA::DIG::TempSensADC2;
const Reg TempSensADC3 = PHA::DIG::TempSensADC3;
const Reg TempSensADC4 = PHA::DIG::TempSensADC4;
const Reg TempSensADC5 = PHA::DIG::TempSensADC5;
const Reg TempSensADC6 = PHA::DIG::TempSensADC6;
const Reg TempSensADC7 = PHA::DIG::TempSensADC7;
const std::vector<Reg> TempSensADC = {TempSensADC0,TempSensADC1,TempSensADC2,TempSensADC3,TempSensADC4,TempSensADC5,TempSensADC6,TempSensADC7};
const std::vector<Reg> TempSensOthers = {TempSensAirIn,TempSensAirOut,TempSensCore,TempSensFirstADC,TempSensLastADC,TempSensHottestADC};
const Reg TempSensDCDC = PHA::DIG::TempSensDCDC;
const Reg VInSensDCDC = PHA::DIG::VInSensDCDC;
const Reg VOutSensDCDC = PHA::DIG::VOutSensDCDC;
const Reg IOutSensDCDC = PHA::DIG::IOutSensDCDC;
const Reg FreqSensCore = PHA::DIG::FreqSensCore;
const Reg DutyCycleSensDCDC = PHA::DIG::DutyCycleSensDCDC;
const Reg SpeedSensFan1 = PHA::DIG::SpeedSensFan1;
const Reg SpeedSensFan2 = PHA::DIG::SpeedSensFan2;
const Reg ErrorFlags = PHA::DIG::ErrorFlags;
const Reg BoardReady = PHA::DIG::BoardReady;
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
const Reg SPFLinkPresence = PHA::DIG::SPFLinkPresence;
const Reg SPFLinkActive = PHA::DIG::SPFLinkActive;
const Reg SPFLinkProtocol = PHA::DIG::SPFLinkProtocol;
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
///============= read write
//const Reg EnableClockOutBackplane ("EnClockOutP0", RW::ReadWrite, TYPE::DIG);
const Reg ClockSource = PHA::DIG::ClockSource;
const Reg IO_Level = PHA::DIG::IO_Level;
const Reg StartSource = PHA::DIG::StartSource;
const Reg GlobalTriggerSource = PHA::DIG::GlobalTriggerSource;
const Reg BusyInSource = PHA::DIG::BusyInSource;
const Reg EnableClockOutFrontPanel = PHA::DIG::EnableClockOutFrontPanel;
const Reg TrgOutMode = PHA::DIG::TrgOutMode;
const Reg GPIOMode = PHA::DIG::GPIOMode;
const Reg SyncOutMode = PHA::DIG::SyncOutMode;
const Reg BoardVetoSource = PHA::DIG::BoardVetoSource;
const Reg BoardVetoWidth = PHA::DIG::BoardVetoWidth;
const Reg BoardVetoPolarity = PHA::DIG::BoardVetoPolarity;
const Reg RunDelay = PHA::DIG::RunDelay;
const Reg EnableAutoDisarmACQ = PHA::DIG::EnableAutoDisarmACQ;
const Reg EnableDataReduction = PHA::DIG::EnableDataReduction;
const Reg EnableStatisticEvents = PHA::DIG::EnableStatisticEvents;
const Reg VolatileClockOutDelay = PHA::DIG::VolatileClockOutDelay;
const Reg PermanentClockOutDelay = PHA::DIG::PermanentClockOutDelay;
const Reg TestPulsePeriod = PHA::DIG::TestPulsePeriod;
const Reg TestPulseWidth = PHA::DIG::TestPulseWidth;
const Reg TestPulseLowLevel = PHA::DIG::TestPulseLowLevel;
const Reg TestPulseHighLevel = PHA::DIG::TestPulseHighLevel;
const Reg ErrorFlagMask = PHA::DIG::ErrorFlagMask;
const Reg ErrorFlagDataMask = PHA::DIG::ErrorFlagDataMask;
const Reg DACoutMode = PHA::DIG::DACoutMode;
const Reg DACoutStaticLevel = PHA::DIG::DACoutStaticLevel;
const Reg DACoutChSelect = PHA::DIG::DACoutChSelect;
const Reg EnableOffsetCalibration = PHA::DIG::EnableOffsetCalibration;
const Reg ITLAMainLogic = PHA::DIG::ITLAMainLogic;
const Reg ITLAMajorityLev = PHA::DIG::ITLAMajorityLev;
const Reg ITLAPairLogic = PHA::DIG::ITLAPairLogic;
const Reg ITLAPolarity = PHA::DIG::ITLAPolarity;
const Reg ITLAMask = PHA::DIG::ITLAMask;
const Reg ITLAGateWidth = PHA::DIG::ITLAGateWidth;
const Reg ITLBMainLogic = PHA::DIG::ITLBMainLogic;
const Reg ITLBMajorityLev = PHA::DIG::ITLBMajorityLev;
const Reg ITLBPairLogic = PHA::DIG::ITLBPairLogic;
const Reg ITLBPolarity = PHA::DIG::ITLBPolarity;
const Reg ITLBMask = PHA::DIG::ITLBMask;
const Reg ITLBGateWidth = PHA::DIG::ITLBGateWidth;
const Reg LVDSIOReg = PHA::DIG::LVDSIOReg;
//const Reg LVDSTrgMask ("lvdstrgmask", RW::ReadWrite, TYPE::DIG, {}, ANSTYPE::BYTE, "64-bit");
/// ========== command
const Reg Reset = PHA::DIG::Reset;
const Reg ClearData = PHA::DIG::ClearData;
const Reg ArmACQ = PHA::DIG::ArmACQ;
const Reg DisarmACQ = PHA::DIG::DisarmACQ;
const Reg SoftwareStartACQ = PHA::DIG::SoftwareStartACQ;
const Reg SoftwareStopACQ = PHA::DIG::SoftwareStopACQ;
const Reg SendSoftwareTrigger = PHA::DIG::SendSoftwareTrigger;
const Reg ReloadCalibration = PHA::DIG::ReloadCalibration;
const std::vector<Reg> AllSettings = {
CupVer ,
FPGA_firmwareVersion ,
FirmwareType ,
ModelCode ,
PBCode ,
ModelName ,
FromFactor ,
FamilyCode ,
SerialNumber ,
PCBrev_MB ,
PCBrev_PB ,
DPP_License ,
DPP_LicenseStatus ,
DPP_LicenseRemainingTime ,
NumberOfChannel ,
ADC_bit ,
ADC_SampleRate ,
InputDynamicRange ,
InputType ,
InputImpedance ,
IPAddress ,
NetMask ,
Gateway ,
LED_status ,
ACQ_status ,
MaxRawDataSize ,
TempSensAirIn ,
TempSensAirOut ,
TempSensCore ,
TempSensFirstADC ,
TempSensLastADC ,
TempSensHottestADC ,
TempSensADC0 ,
TempSensADC1 ,
TempSensADC2 ,
TempSensADC3 ,
TempSensADC4 ,
TempSensADC5 ,
TempSensADC6 ,
TempSensADC7 ,
TempSensDCDC ,
VInSensDCDC ,
VOutSensDCDC ,
IOutSensDCDC ,
FreqSensCore ,
DutyCycleSensDCDC ,
SpeedSensFan1 ,
SpeedSensFan2 ,
ErrorFlags ,
BoardReady ,
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
// SPFLinkPresence ,
// SPFLinkActive ,
// SPFLinkProtocol ,
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
ClockSource ,
IO_Level ,
StartSource ,
GlobalTriggerSource ,
BusyInSource ,
//EnableClockOutBackplane ,
EnableClockOutFrontPanel ,
TrgOutMode ,
GPIOMode ,
SyncOutMode ,
BoardVetoSource ,
BoardVetoWidth ,
BoardVetoPolarity ,
RunDelay ,
EnableAutoDisarmACQ ,
EnableDataReduction ,
EnableStatisticEvents ,
VolatileClockOutDelay ,
PermanentClockOutDelay ,
TestPulsePeriod ,
TestPulseWidth ,
TestPulseLowLevel ,
TestPulseHighLevel ,
ErrorFlagMask ,
ErrorFlagDataMask ,
DACoutMode ,
DACoutStaticLevel ,
DACoutChSelect ,
EnableOffsetCalibration ,
ITLAMainLogic ,
ITLAMajorityLev ,
ITLAPairLogic ,
ITLAPolarity ,
ITLAMask ,
ITLAGateWidth ,
ITLBMainLogic ,
ITLBMajorityLev ,
ITLBPairLogic ,
ITLBPolarity ,
ITLBMask ,
ITLBGateWidth ,
LVDSIOReg
//LVDSTrgMask
};
}
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
namespace GROUP{
const Reg InputDelay = PHA::GROUP::InputDelay;
}
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
namespace VGA{
const Reg VGAGain = PHA::VGA::VGAGain;
}
namespace LVDS{
const Reg LVDSMode = PHA::LVDS::LVDSMode;
const Reg LVDSDirection = PHA::LVDS::LVDSDirection;
const std::vector<Reg> AllSettings = {
LVDSMode ,
LVDSDirection
};
}
namespace CH{
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
/// ========= command
const Reg SendChSWTrigger ("SendChSWrigger", RW::WriteOnly, TYPE::CH, {}, ANSTYPE::NONE, "", true);
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
/// ========= red only
const Reg SelfTrgRate = PHA::CH::SelfTrgRate;
const Reg ChannelStatus = PHA::CH::ChannelStatus;
const Reg GainFactor = PHA::CH::GainFactor;
const Reg ADCToVolts = PHA::CH::ADCToVolts;
const Reg ChannelRealtime = PHA::CH::ChannelRealtime;
const Reg ChannelDeadtime = PHA::CH::ChannelDeadtime;
const Reg ChannelTriggerCount = PHA::CH::ChannelTriggerCount;
const Reg ChannelSavedCount = PHA::CH::ChannelSavedCount;
const Reg ChannelWaveCount = PHA::CH::ChannelWaveCount;
/// ======= read write
added InputDelay for latest firmware
2023-10-25 14:57:07 -04:00
//^ not impletemented
const Reg SelfTriggerWidth = PHA::CH::SelfTriggerWidth;
const Reg SignalOffset = PHA::CH::SignalOffset;
//^ impletemented
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
const Reg ChannelEnable = PHA::CH::ChannelEnable;
const Reg DC_Offset = PHA::CH::DC_Offset;
const Reg TriggerThreshold = PHA::CH::TriggerThreshold;
const Reg Polarity = PHA::CH::Polarity;
const Reg WaveDataSource = PHA::CH::WaveDataSource;
const Reg RecordLength = PHA::CH::RecordLength;
const Reg PreTrigger = PHA::CH::PreTrigger;
const Reg WaveSaving = PHA::CH::WaveSaving;
const Reg WaveResolution = PHA::CH::WaveResolution;
const Reg WaveAnalogProbe0 ("WaveAnalogProbe0", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
{"ADCInputBaseline", "ADC Input baseline"},
{"CFDFilter", "CFD Filter"}});
const Reg WaveAnalogProbe1 ("WaveAnalogProbe1", RW::ReadWrite, TYPE::CH, {{"ADCInput", "ADC Input"},
{"ADCInputBaseline", "ADC Input baseline"},
{"CFDFilter", "CFD Filter"}});
const Reg WaveDigitalProbe0 ("WaveDigitalProbe0", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"CFDFilterArmed", "CFD Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
{"ADCInputOverthreshold", "ADC Input Over-threshold"},
{"ChargeReady", "Charge Ready"},
{"LongGate", "Long Gate"},
{"ShortGate", "Short Gate"},
{"PileUpTrigger", "Pile-up Trig."},
{"ChargeOverRange", "Charge Over Range"},
{"ADCSaturation", "ADC Saturate"},
{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
const Reg WaveDigitalProbe1 ("WaveDigitalProbe1", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"CFDFilterArmed", "CFD Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
{"ADCInputOverthreshold", "ADC Input Over-threshold"},
{"ChargeReady", "Charge Ready"},
{"LongGate", "Long Gate"},
{"ShortGate", "Short Gate"},
{"PileUpTrigger", "Pile-up Trig."},
{"ChargeOverRange", "Charge Over Range"},
{"ADCSaturation", "ADC Saturate"},
{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
const Reg WaveDigitalProbe2 ("WaveDigitalProbe2", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"CFDFilterArmed", "CFD Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
{"ADCInputOverthreshold", "ADC Input Over-threshold"},
{"ChargeReady", "Charge Ready"},
{"LongGate", "Long Gate"},
{"ShortGate", "Short Gate"},
{"PileUpTrigger", "Pile-up Trig."},
{"ChargeOverRange", "Charge Over Range"},
{"ADCSaturation", "ADC Saturate"},
{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
const Reg WaveDigitalProbe3 ("WaveDigitalProbe3", RW::ReadWrite, TYPE::CH, {{"Trigger", "Trigger"},
{"CFDFilterArmed", "CFD Filter Armed"},
{"ReTriggerGuard", "ReTrigger Guard"},
{"ADCInputBaselineFreeze", "ADC Input basline Freeze"},
{"ADCInputOverthreshold", "ADC Input Over-threshold"},
{"ChargeReady", "Charge Ready"},
{"LongGate", "Long Gate"},
{"ShortGate", "Short Gate"},
{"PileUpTrigger", "Pile-up Trig."},
{"ChargeOverRange", "Charge Over Range"},
{"ADCSaturation", "ADC Saturate"},
{"ADCInputNegativeOverthreshold", "ADC Input Neg. Over-Threshold"} });
const std::vector<Reg> AnalogProbe = {WaveAnalogProbe0, WaveAnalogProbe1};
const std::vector<Reg> DigitalProbe = {WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3};
const Reg EventTriggerSource = PHA::CH::EventTriggerSource;
const Reg ChannelsTriggerMask = PHA::CH::ChannelsTriggerMask;
const Reg ChannelVetoSource = PHA::CH::ChannelVetoSource;
const Reg WaveTriggerSource = PHA::CH::WaveTriggerSource;
const Reg EventSelector = PHA::CH::EventSelector;
const Reg WaveSelector = PHA::CH::WaveSelector;
const Reg CoincidenceMask = PHA::CH::CoincidenceMask;
const Reg AntiCoincidenceMask = PHA::CH::AntiCoincidenceMask;
const Reg CoincidenceLength = PHA::CH::CoincidenceLength;
const Reg CoincidenceLengthSample = PHA::CH::CoincidenceLengthSample;
const Reg ADCVetoWidth = PHA::CH::ADCVetoWidth;
const Reg EventNeutronReject ("EventNeutronReject", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},{"Enabled", "Enabled"}});
const Reg WaveNeutronReject ("WaveNeutronReject", RW::ReadWrite, TYPE::CH, {{"Disabled", "Disabled"},{"Enabled", "Enabled"}});
const Reg EnergySkimLowDiscriminator = PHA::CH::EnergySkimLowDiscriminator;
const Reg EnergySkimHighDiscriminator = PHA::CH::EnergySkimHighDiscriminator;
const Reg RecordLengthSample = PHA::CH::RecordLengthSample;
const Reg PreTriggerSample = PHA::CH::PreTriggerSample;
const Reg ITLConnect = PHA::CH::ITLConnect;
const Reg ADCInputBaselineAvg ("ADCInputBaselineAvg", RW::ReadWrite, TYPE::CH, {{"Fixed", "Fixed"},
{"Low", "Low"},
{"MediumLow", "MediumLow"},
{"MediumHigh", "MediumHigh"},
{"High", "High"}});
const Reg AbsoluteBaseline ("AbsoluteBaseline", RW::ReadWrite, TYPE::CH, {{"0", ""},{"65535", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg ADCInputBaselineGuard ("ADCInputBaselineGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg SmoothingFactor ("SmoothingFactor", RW::ReadWrite, TYPE::CH, {{"1", "Disabled"},
{"2", "Avg. 2 samples"},
{"4", "Avg. 4 samples"},
{"8", "Avg. 8 samples"},
{"16", "Avg. 16 samples"}});
const Reg ChargeSmoothing ("ChargeSmoothing", RW::ReadWrite, TYPE::CH, {{"Enabled", "Enabled"}, {"Disabled", "Disabled"}});
const Reg TimeFilterSmoothing ("TimeFilterSmoothing", RW::ReadWrite, TYPE::CH, {{"Enabled", "Enabled"}, {"Disabled", "Disabled"}});
const Reg TriggerFilterSelection ("TriggerFilterSelection", RW::ReadWrite, TYPE::CH, {{"LeadingEdge", "Leading Edge"}, {"CFD", "CFD"}});
const Reg CFDDelay ("CFDDelayT", RW::ReadWrite, TYPE::CH, {{"32", ""},{"8184", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg CFDFraction ("CFDFraction", RW::ReadWrite, TYPE::CH, {{"25", ""},{"100", ""},{"0", ""}}, ANSTYPE::INTEGER, "%");
const Reg TimeFilterRetriggerGuard ("TimeFilterRetriggerGuardT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg TriggerHysteresis ("TriggerHysteresis", RW::ReadWrite, TYPE::CH, {{"Enabled", "Enabled"}, {"Disabled", "Disabled"}});
const Reg PileupGap ("PileupGap", RW::ReadWrite, TYPE::CH, {{"0", ""},{"65535", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg GateLongLength ("GateLongLengthT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"32000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg GateShortLength ("GateShortLengthT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"32000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg GateOffset ("GateOffsetT", RW::ReadWrite, TYPE::CH, {{"0", ""},{"2000", ""},{"8", ""}}, ANSTYPE::INTEGER, "ns");
const Reg LongChargeIntegratorPedestal ("LongChargeIntegratorPedestal", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "count");
const Reg ShortChargeIntegratorPedestal ("ShortChargeIntegratorPedestal", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "count");
add PSD supper in the Scope. Issue, the trace don't change after few sec for PSD, not PHA. firmware problem?
2023-09-25 17:07:17 -04:00
const Reg EnergyGain ("EnergyGain", RW::ReadWrite, TYPE::CH, {{"x1", "No Gain"},
{"x4", "x4"},
{"x16", "x16"},
{"x64", "x64"},
{"x256", "x256"}});
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
const Reg NeutronThreshold ("NeutronThreshold", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "count");
const Reg ADCInputBaselineGuardSample ("ADCInputBaselineGuardS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"1000", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg CFDDelaySample ("CFDDelayS", RW::ReadWrite, TYPE::CH, {{"4", ""},{"1023", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
add PSD in the core Digitizer Class and SolReader
2023-09-22 15:58:28 -04:00
const Reg TimeFilterRetriggerGuardSample ("TimeFilterRetriggerGuardS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"8000", ""},{"8", ""}}, ANSTYPE::INTEGER, "sample");
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
const Reg GateLongLengthSample ("GateLongLengthS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"4000", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg GateShortLengthSample ("GateShortLengthS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"4000", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
const Reg GateOffsetSample ("GateOffsetS", RW::ReadWrite, TYPE::CH, {{"0", ""},{"250", ""},{"1", ""}}, ANSTYPE::INTEGER, "sample");
const std::vector<Reg> AllSettings = {
add PSD in the core Digitizer Class and SolReader
2023-09-22 15:58:28 -04:00
SelfTrgRate , // 0
fix ReadData logic problem
2023-09-22 17:57:43 -04:00
ChannelStatus , // 1
GainFactor , // 2
ADCToVolts , // 3
ChannelRealtime , // 4
ChannelDeadtime , // 5
ChannelTriggerCount , // 6
ChannelSavedCount , // 7
ChannelWaveCount , // 8
ChannelEnable , // 0
DC_Offset , // 1
TriggerThreshold , // 2
Polarity , // 3
WaveDataSource , // 4
RecordLength , // 5
PreTrigger , // 6
WaveSaving , // 7
WaveResolution , // 8
EventTriggerSource , // 9
ChannelsTriggerMask , // 10
ChannelVetoSource , // 11
WaveTriggerSource , // 12
EventSelector , // 13
WaveSelector , // 14
CoincidenceMask , // 15
AntiCoincidenceMask , // 16
CoincidenceLength , // 17
ADCVetoWidth , // 18
EnergySkimLowDiscriminator , // 19
EnergySkimHighDiscriminator, // 20
ITLConnect , // 21
EventNeutronReject ,
WaveNeutronReject ,
ADCInputBaselineAvg ,
AbsoluteBaseline ,
ADCInputBaselineGuard ,
SmoothingFactor ,
ChargeSmoothing ,
TimeFilterSmoothing ,
TriggerFilterSelection ,
CFDDelay ,
CFDFraction ,
TimeFilterRetriggerGuard ,
TriggerHysteresis ,
PileupGap ,
GateLongLength ,
GateShortLength ,
GateOffset ,
add PSD in the core Digitizer Class and SolReader
2023-09-22 15:58:28 -04:00
LongChargeIntegratorPedestal, //
ShortChargeIntegratorPedestal, //
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
EnergyGain ,
NeutronThreshold ,
fix ReadData logic problem
2023-09-22 17:57:43 -04:00
WaveAnalogProbe0 , //
WaveAnalogProbe1 , //
WaveDigitalProbe0 , //
WaveDigitalProbe1 , //
WaveDigitalProbe2 , //
remove settings using Sample in setting file
2023-10-19 09:38:57 -04:00
WaveDigitalProbe3 //,
// RecordLengthSample , // 21
// PreTriggerSample , // 22
// CoincidenceLengthSample , //
// ADCInputBaselineGuardSample,
// CFDDelaySample ,
// TimeFilterRetriggerGuardSample,
// GateLongLengthSample ,
// GateShortLengthSample ,
// GateOffsetSample
added PSD prarmeeters
2023-09-21 19:00:48 -04:00
};
}
};
added DigiPrarameters.h
2023-02-08 17:35:04 -05:00
#endif
Reference in New Issue Copy Permalink