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add CupVer protection for Input Delay setting

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This commit is contained in:
Ryan Tang 2023-10-25 15:06:33 -04:00
parent 7c1314d009
commit c215d3cea1
3 changed files with 29 additions and 20 deletions
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39
ClassDigitizer2Gen.cpp
View File

@ -26,6 +26,7 @@ void Digitizer2Gen::Initialization(){
FPGAType = ""; FPGAType = "";
nChannels = 0; nChannels = 0;
ch2ns = 0; ch2ns = 0;
CupVer = 0;
outFileIndex = 0; outFileIndex = 0;
FinishedOutFilesSize = 0; FinishedOutFilesSize = 0;
@ -235,6 +236,7 @@ int Digitizer2Gen::OpenDigitizer(const char * url){
FPGAVer = atoi(ReadValue(PHA::DIG::CupVer).c_str()); FPGAVer = atoi(ReadValue(PHA::DIG::CupVer).c_str());
nChannels = atoi(ReadValue(PHA::DIG::NumberOfChannel).c_str()); nChannels = atoi(ReadValue(PHA::DIG::NumberOfChannel).c_str());
ModelName = ReadValue(PHA::DIG::ModelName); ModelName = ReadValue(PHA::DIG::ModelName);
CupVer = atoi(ReadValue(PHA::DIG::CupVer).c_str());
int adcRate = atoi(ReadValue(PHA::DIG::ADC_SampleRate).c_str()); int adcRate = atoi(ReadValue(PHA::DIG::ADC_SampleRate).c_str());
ch2ns = 1000/adcRate; ch2ns = 1000/adcRate;
@ -1079,10 +1081,12 @@ void Digitizer2Gen::PrintBoardSettings(){
} }
} }
for(int idx = 0; idx < 16 ; idx ++ ){ if( CupVer >= 2023091800 ){
printf("%-45s %d %s\n", InputDelay[idx].GetFullPara(idx).c_str(), for(int idx = 0; idx < 16 ; idx ++ ){
InputDelay[idx].ReadWrite(), printf("%-45s %d %s\n", InputDelay[idx].GetFullPara(idx).c_str(),
InputDelay[idx].GetValue().c_str()); InputDelay[idx].ReadWrite(),
InputDelay[idx].GetValue().c_str());
}
} }
for( int i = 0; i < (int) LVDSSettings[0].size(); i++){ for( int i = 0; i < (int) LVDSSettings[0].size(); i++){
@ -1144,7 +1148,7 @@ void Digitizer2Gen::ReadAllSettings(){
if( ModelName == "VX2745") for(int i = 0; i < 4 ; i ++) ReadValue(VGASetting[i], i); if( ModelName == "VX2745") for(int i = 0; i < 4 ; i ++) ReadValue(VGASetting[i], i);
for( int idx = 0; idx < 16; idx++) ReadValue(InputDelay[idx], idx, false); if( CupVer >= 2023091800 ) for( int idx = 0; idx < 16; idx++) ReadValue(InputDelay[idx], idx, false);
for( int index = 0; index < 4; index++){ for( int index = 0; index < 4; index++){
for( int i = 0; i < (int) LVDSSettings[index].size(); i++){ for( int i = 0; i < (int) LVDSSettings[index].size(); i++){
@ -1202,18 +1206,19 @@ int Digitizer2Gen::SaveSettingsToFile(const char * saveFileName, bool setReadOnl
count ++; count ++;
} }
for( int idx = 0; idx < 16; idx ++){ if( CupVer >= 2023091800 ){
totCount ++; for( int idx = 0; idx < 16; idx ++){
if( InputDelay[idx].GetValue() == "" ) { totCount ++;
printf(" No value for %s \n", InputDelay[idx].GetPara().c_str()); if( InputDelay[idx].GetValue() == "" ) {
continue; printf(" No value for %s \n", InputDelay[idx].GetPara().c_str());
continue;
}
fprintf(saveFile, "%-45s!%d!%4d!%s\n", InputDelay[idx].GetFullPara(idx).c_str(),
InputDelay[idx].ReadWrite(),
9050 + idx,
InputDelay[idx].GetValue().c_str());
count ++;
} }
fprintf(saveFile, "%-45s!%d!%4d!%s\n", InputDelay[idx].GetFullPara(idx).c_str(),
InputDelay[idx].ReadWrite(),
9050 + idx,
InputDelay[idx].GetValue().c_str());
count ++;
} }
if( ModelName == "VX2745" && FPGAType == DPPType::PHA) { if( ModelName == "VX2745" && FPGAType == DPPType::PHA) {
@ -1350,7 +1355,7 @@ bool Digitizer2Gen::LoadSettingsFromFile(const char * loadFileName){
}else if ( 9000 <= id && id < 9050){ // vga }else if ( 9000 <= id && id < 9050){ // vga
VGASetting[id - 9000].SetValue(value); VGASetting[id - 9000].SetValue(value);
}else{ // group }else{ // group
InputDelay[id - 9050].SetValue(value); if( CupVer >= 2023091800 ) InputDelay[id - 9050].SetValue(value);
} }
//printf("%s|%s|%d|%s|\n", para, readWrite, id, value); //printf("%s|%s|%d|%s|\n", para, readWrite, id, value);
if( std::strcmp(readWrite, "2") == 0 && isConnected) WriteValue(para, value, false); if( std::strcmp(readWrite, "2") == 0 && isConnected) WriteValue(para, value, false);

2
ClassDigitizer2Gen.h
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@ -33,6 +33,7 @@ class Digitizer2Gen {
char retValue[256]; char retValue[256];
unsigned short serialNumber; unsigned short serialNumber;
unsigned int CupVer;
std::string FPGAType; // look the DigitiParameter.h::PHA::DIG::FirwareType, DPP_PHA, DPP_ZLE, DPP_PSD, DPP_DAW, DPP_OPEN, and Scope std::string FPGAType; // look the DigitiParameter.h::PHA::DIG::FirwareType, DPP_PHA, DPP_ZLE, DPP_PSD, DPP_DAW, DPP_OPEN, and Scope
unsigned int FPGAVer; // for checking copy setting unsigned int FPGAVer; // for checking copy setting
unsigned short nChannels; unsigned short nChannels;
@ -77,6 +78,7 @@ class Digitizer2Gen {
std::string GetFPGAType() const {return FPGAType;} std::string GetFPGAType() const {return FPGAType;}
std::string GetModelName() const {return ModelName;} std::string GetModelName() const {return ModelName;}
unsigned int GetFPGAVersion() const {return FPGAVer;} unsigned int GetFPGAVersion() const {return FPGAVer;}
unsigned int GetCupVer() const {return CupVer;}
void SetDummy(unsigned short sn); void SetDummy(unsigned short sn);
bool IsDummy() const {return isDummy;} bool IsDummy() const {return isDummy;}

6
digiSettingsPanel.cpp
View File

@ -788,7 +788,8 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
} }
{//^====================== Group = InputDelay if( digi[iDigi]->GetCupVer() >= 2023091800 ){
//^====================== Group = InputDelay
bdGroup[iDigi] = new QWidget(this); bdGroup[iDigi] = new QWidget(this);
bdTab->addTab(bdGroup[iDigi], "Input Delay"); bdTab->addTab(bdGroup[iDigi], "Input Delay");
QGridLayout * groupLayout = new QGridLayout(bdGroup[iDigi]); QGridLayout * groupLayout = new QGridLayout(bdGroup[iDigi]);
@ -800,7 +801,8 @@ DigiSettingsPanel::DigiSettingsPanel(Digitizer2Gen ** digi, unsigned short nDigi
spbInputDelay[iDigi][k]->setDecimals(6); spbInputDelay[iDigi][k]->setDecimals(6);
} }
}else{
bdGroup[iDigi] = nullptr;
} }
} }