156 lines
6.7 KiB
C
156 lines
6.7 KiB
C
#ifndef REGISTERADDRESS_H
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#define REGISTERADDRESS_H
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enum class Register : uint32_t {
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EventReadOutBuffer = 0x0000, /// R
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///========== Channel or Group
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ChannelDummy32 = 0x1024, /// R/W
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InputDynamicRange = 0x1028, /// R/W
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ChannelPulseWidth = 0x1070, /// R/W
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ChannelTriggerThreshold = 0x1080, /// R/W
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CoupleSelfTriggerLogic = 0x1084, /// R/W
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ChannelStatus = 0x1088, /// R
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AMCFirmwareRevision = 0x108C, /// R
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ChannelDCOffset = 0x1098, /// R/W
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ChannelADCTemperature = 0x10A8, /// R
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ChannelSelfTriggerRateMeter = 0x10EC, /// R
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///========== Board
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BoardConfiguration = 0x8000, /// R/W
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BufferOrganization = 0x800C, /// R/W
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CustomSize = 0x8020, /// R/W
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ADCCalibration = 0x809C, /// W
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AcquisitionControl = 0x8100, /// R/W
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AcquisitionStatus = 0x8104, /// R
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SoftwareTrigger = 0x8108, /// W
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GlobalTriggerMask = 0x810C, /// R/W
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FrontPanelTRGOUTEnableMask = 0x8110, /// R/W
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PostTrigger = 0x8114, /// R/W
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LVDSIOData = 0x8118, /// R/W
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FrontPanelIOControl = 0x811C, /// R/W
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ChannelEnableMask = 0x8120, /// R/W
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ROCFPGAFirmwareRevision = 0x8124, /// R
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EventStored = 0x812C, /// R
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VoltageLevelModeConfig = 0x8138, /// R/W
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SoftwareClockSync = 0x813C, /// W
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BoardInfo = 0x8140, /// R
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AnalogMonitorMode = 0x8144, /// R/W
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EventSize = 0x814C, /// R
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FanSpeedControl = 0x8168, /// R/W
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MemoryBufferAlmostFullLevel = 0x816C, /// R/W
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RunStartStopDelay = 0x8170, /// R/W
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BoardFailureStatus = 0x8178, /// R
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FrontPanelLVDSIONewFeatures = 0x81A0, /// R/W
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BufferOccupancyGain = 0x81B4, /// R/W
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ChannelsShutdown = 0x81C0, /// W
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ExtendedVetoDelay = 0x81C4, /// R/W
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ReadoutControl = 0xEF00, /// R/W
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ReadoutStatus = 0xEF04, /// R
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BoardID = 0xEF08, /// R/W
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MCSTBaseAddressAndControl = 0xEF0C, /// R/W
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RelocationAddress = 0xEF10, /// R/W
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InterruptStatusID = 0xEF14, /// R/W
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InterruptEventNumber = 0xEF18, /// R/W
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MaxNumberOfEventsPerBLT = 0xEF1C, /// R/W
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Scratch = 0xEF20, /// R/W
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SoftwareReset = 0xEF24, /// W
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SoftwareClear = 0xEF28 /// W
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};
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///====== Common for PHA and PSD
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enum class RegisterDPP : uint32_t {
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RecordLength = 0x1020, /// R/W
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InputDynamicRange = 0x1028, /// R/W
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NumberEventsPerAggregate = 0x1034, /// R/W
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PreTrigger = 0x1038, /// R/W
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TriggerThreshold = 0x106C, /// R/W
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TriggerHoldOffWidth = 0x1074, /// R/W
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DPPAlgorithmControl = 0x1080, /// R/W
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ChannelStatus = 0x1088, /// R
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AMCFirmwareRevision = 0x108C, /// R
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ChannelDCOffset = 0x1098, /// R/W
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ChannelADCTemperature = 0x10A8, /// R
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IndividualSoftwareTrigger = 0x10C0, /// W
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VetoWidth = 0x10D4, /// R/W
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BoardConfiguration = 0x8000, /// R/W
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AggregateOrganization = 0x800C, /// R/W
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ADCCalibration = 0x809C, /// W
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ChannelShutdown = 0x80BC, /// W
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AcquisitionControl = 0x8100, /// R/W
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AcquisitionStatus = 0x8104, /// R
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SoftwareTrigger = 0x8108, /// W
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GlobalTriggerMask = 0x810C, /// R/W
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FrontPanelTRGOUTEnableMask = 0x8110, /// R/W
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LVDSIOData = 0x8118, /// R/W
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FrontPanelIOControl = 0x811C, /// R/W
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ChannelEnableMask = 0x8120, /// R/W
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ROCFPGAFirmwareRevision = 0x8124, /// R
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EventStored = 0x812C, /// R
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VoltageLevelModeConfig = 0x8138, /// R/W
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SoftwareClockSync = 0x813C, /// W
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BoardInfo = 0x8140, /// R
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AnalogMonitorMode = 0x8144, /// R/W
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EventSize = 0x814C, /// R
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TimeBombDowncounter = 0x8158, /// R
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FanSpeedControl = 0x8168, /// R/W
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RunStartStopDelay = 0x8170, /// R/W
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BoardFailureStatus = 0x8178, /// R
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DisableExternalTrigger = 0x817C, /// R/W
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TriggerValidationMask = 0x8180, /// R/W, 0x8180 + 4n
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FrontPanelLVDSIONewFeatures = 0x81A0, /// R/W
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BufferOccupancyGain = 0x81B4, /// R/W
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ExtendedVetoDelay = 0x81C4, /// R/W
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ReadoutControl = 0xEF00, /// R/W
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ReadoutStatus = 0xEF04, /// R
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BoardID = 0xEF08, /// R/W
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MCSTBaseAddressAndControl = 0xEF0C, /// R/W
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RelocationAddress = 0xEF10, /// R/W
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InterruptStatusID = 0xEF14, /// R/W
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InterruptEventNumber = 0xEF18, /// R/W
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MaxNumberOfEventsPerBLT = 0xEF1C, /// R/W
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Scratch = 0xEF20, /// R/W
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SoftwareReset = 0xEF24, /// W
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SoftwareClear = 0xEF28 /// W
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};
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enum class RegisterPHA : uint32_t {
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DataFlush = 0x103C, /// W not sure
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ChannelStopAcquisition = 0x1040, /// R/W not sure
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RCCR2SmoothingFactor = 0x1054, /// R/W Trigger Filter smoothing, triggerSmoothingFactor
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InputRiseTime = 0x1058, /// R/W OK
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TrapezoidRiseTime = 0x105C, /// R/W OK
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TrapezoidFlatTop = 0x1060, /// R/W OK
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PeakingTime = 0x1064, /// R/W OK
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DecayTime = 0x1068, /// R/W OK
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TriggerThreshold = 0x106C, /// R/W OK
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RiseTimeValidationWindow = 0x1070, /// R/W OK
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TriggerHoldOffWidth = 0x1074, /// R/W OK
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PeakHoldOff = 0x1078, /// R/W OK
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ShapedTriggerWidth = 0x1084, /// R/W not sure
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DPPAlgorithmControl2 = 0x10A0, /// R/W OK
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FineGain = 0x10C4, /// R/W OK
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};
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enum class RegisterPSD : uint32_t {
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CFDSetting = 0x103C, /// R/W
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ForcedDataFlush = 0x1040, /// W
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ChargeZeroSuppressionThreshold = 0x1044, /// R/W
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ShortGateWidth = 0x1054, /// R/W
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LongGateWidth = 0x1058, /// R/W
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GateOffset = 0x105C, /// R/W
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TriggerThreshold = 0x1060, /// R/W
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FixedBaseline = 0x1064, /// R/W
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TriggerLatency = 0x106C, /// R/W
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ShapedTriggerWidth = 0x1070, /// R/W
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TriggerHoldOffWidth = 0x1074, /// R/W
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ThresholdForPSDCut = 0x1078, /// R/W
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PureGapThreshold = 0x107C, /// R/W
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DPPAlgorithmControl2 = 0x1084, /// R/W
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EarlyBaselineFreeze = 0x10D8, /// R/W
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};
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#endif
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